Data processing system using internet protocols

• US 20040037299A1
• Filed: 06/10/2003
• Published: 02/26/2004
• Est. Priority Date: 06/11/2002
• Status: Active Grant

• Current Assignee: Memory Access Technologies LLC
• Original Assignee: Ashish A. Pandya
• Inventors: Pandya, Ashish A.
• Granted Patent: US 8,005,966 B2
• Time in Patent Office: Days
• US Class Current: 370/401
• CPC Class Codes: H04L 67/1097 for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
• CPC Class Codes: H04L 67/34 involving the movement of software or configuration parameters network booting or remote initial program loading [RIPL] G06F9/4416
• CPC Class Codes: H04L 69/10 Streamlined, light-weight or high-speed protocols, e.g. express transfer protocol [XTP] or byte stream
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 69/163 In-band adaptation of TCP data exchange; In-band control procedures
• CPC Class Codes: H04L 69/165 Combined use of TCP and UDP protocols; selection criteria therefor
• CPC Class Codes: H04L 69/166 IP fragmentation; TCP segmentation
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
• CPC Class Codes: H04L 69/32 Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
• CPC Class Codes: H04L 69/323 in the physical layer [OSI layer 1]
• CPC Class Codes: H04L 69/326 in the transport layer [OSI layer 4] H04L69/16 takes precedence
• CPC Class Codes: H04L 69/329 in the application layer [OSI layer 7]
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

Disclosed are systems employing an architecture that provides capabilities to transport and process Internet Protocol (IP) packets from Layer 2 through transport protocol processing and may also perform packet inspection through Layer 7. A set of engines may perform pass-through packet classification, policy processing and/or security processing enabling packet streaming through the architecture at nearly the full line rate. A scheduler schedules packets to packet processors for processing. An internal memory or local session database cache stores a session information database for a certain number of active sessions. The session information that is not in the internal memory is stored and retrieved to/from an additional memory.

Claims

1. A host processor having a SCSI command layer and an iSCSI driver, said host processor capable of being coupled to a hardware implemented iSCSI controller useable in high speed storage over IP, said controller for transporting received iSCSI commands and PDUs, said controller having access to a data base for keeping track of data processing operations, said database being in memory on said controller, or in memory partly on said controller and partly in a computing apparatus other than said controller, said controller having a transmit and a receive path for data flow, said controller comprising:

a. a command scheduler for scheduling processing of commands, said scheduler coupled to said SCSI command layer and to said iSCSI driver;

b. a receive path for data flow of received data and a transmit path for data flow of transmitted data;

c. at least one transmit engine for transmitting iSCSI PDUs;

d. at least one transmit command engine for interpreting said PDUs and performing operations including retrieving information from said host processor and keeping command flow information in said database updated as said retrieving progresses;

e. at least one receive command engine; and

f. at least one receive engine for interpreting received commands into requests for at least one of said at least one receive command engine.

2. A switching system comprising a plurality of line cards coupled to a switching fabric, said line cards including a processor for processing Internet data packets in one or more sessions, said processor including a session memory for storing frequently or recently used session information for a plurality of sessions.

3. The switching system of claim 2 wherein said processor on at least one line card includes a host interface functioning as a fabric interface and said switching fabric is coupled to said fabric interface through a fabric controller.

4. The switching system of claim 3 wherein said fabric controller functions as an interface to said switching fabric, as a traffic manager as a traffic shaper or a combination of any of the foregoing.

5. A multiprocessor system comprising at least one data processor coupled to a plurality of IP processors for interfacing said at least one data processor to said IP processors, for enabling TCP, STCP, UDP or other session oriented protocols over IP networks, said IP processor comprising:

a. at least one packet processor for processing IP packets;

b. a session memory for storing IP session information;

c. at least one memory controller for controlling memory accesses;

d. at least one media interface for coupling to at least one network; and

e. a host interface for coupling to a host or fabric interface for coupling to a fabric.

6. The multiprocessor system of claim 5, said IP network application processor further comprising at least one of:

a. an IP Storage session memory for storing IP Storage session information;

b. a classification processor for classifying IP packets;

c. a flow controller for controlling data flow;

d. a policy processor for applying policies;

e. a security processor for performing security operations;

f. a packet memory for storing packets;

g. a controller for control plane processing;

h. a packet scheduler;

i. coprocessor interface for interfacing to a peer processor;

or

a combination of any of the foregoing.

7. The multiprocessor system of claim 5 wherein two or more of said plurality of IP processors are coupled to each other.

8. The multiprocessor system of claim 6 wherein two or more of said plurality of IP processors are coupled to each other.

9. The multiprocessor system of claim 7 wherein said two or more of said plurality of IP processors are coupled through a co-processor interface, or a host interface, or a bridge, or a combination of any of the foregoing.

10. The multiprocessor system of claim 8 wherein said two or more of said plurality of IP processors are coupled through a co-processor interface, or a host interface, or a bridge, or a combination of any of the foregoing.

11. A switching system having a plurality of line cards, each said line card having identification information based therein and comprising a hardware processor providing TCP/IP protocol termination and origination for enabling data transfer using TCP over IP networks, said processor being programmable and sending and receiving data packets also having identification information based therein, said packets transmitted, encapsulated or encoded using a iSCSI, iFCP, infiniband, SATA, SAS, IP, ICMP, IPSEC, DES, 3DES, AES, FC, SCSI, FCIP, NFS, CIFS, DAFS, HTTP, XML, XML derivative, SGML, or HTML format, or a combination of any of the foregoing.

32. The switching system of claim 11 wherein said processor operates on said packets to apply an access control, intrusion detection, bandwidth monitoring, bandwidth management, traffic shaping, security, virus detection, anti-spam, quality of service, encryption, decryption, LUN masking, zoning, multi-pathing, link aggregation or virtualization function or policy or a combination of any of the foregoing.

33. The combination of claim 11 wherein said hardware processor itself includes a processor for performing deep packet inspection and classification.

34. The combination of claim 33 wherein said hardware processor itself includes a processor for performing policy management or policy enforcement on a packet-by-packet basis.

12. A networking appliance comprising a hardware processor providing TCP/IP protocol termination and origination capability for enabling data transfer from and to a data source, to and from a data destination, of data traffic transmitted, encapsulated or encoded using TCP over IP networks, said processor enabling said appliance to transport TCP/IP packets in-band to said data traffic or out of band to said data traffic.

13. The appliance of claim 12 wherein said processor operates on said packets to apply an access control, intrusion detection, bandwidth monitoring, bandwidth management, traffic shaping, security, virus detection, anti-spam, quality of service, encryption, decryption, LUN masking, zoning, multi-pathing, link aggregation or virtualization function or policy or a combination of any of the foregoing.

14. The appliance of claim 12 wherein said processor is programmable and operates on data packets transmitted, encapsulated or encoded using an iSCSI, iFCP, infiniband, SATA, SAS, IP, ICMP, IPSEC, DES, 3DES, AES, FC, SCSI, FCIP, NFS, CIFS, DAFS, HTTP, XML, XML derivative, SGML, or HTML format or a combination of any of the foregoing.

15. The combination of claim 12 wherein said hardware processor itself includes a processor for performing deep packet inspection and classification.

16. The combination of claim 15 wherein said hardware processor itself includes a processor for performing policy management or policy enforcement on a packet-by-packet basis.

17. The combination of claim 16 wherein said hardware processor performs a function of virtualization, policy based management, policy enforcement, operations in-band to said data traffic or operations out of band to said data traffic.

19. The appliance of claim 12 wherein said processor operates on said packets to apply one or more policies on packets and said appliance is located in-band to said traffic to apply one or more policies on packets at substantially the full line rate.

18. A host processor having a mother board, said motherboard having thereon one chip of a chip set, said one chip comprising a programmable hardware processor providing TCP/IP protocol termination and origination capability for enabling data transfer using TCP, SCTP or UDP, or other session oriented protocol or a combination of any of the foregoing over IP networks.

20. A server that is a blade server, thin server, appliance server, unix server, linux server, Windows or Windows derivative server, clustered server, database server, grid computing server, VOIP server, wireless gateway server, security server, file server, network attached server, media server, streaming media server or game server, or a combination of any of the foregoing, said server including a chipset containing a hardware processor providing a TCP/IP protocol termination and origination capability over TCP, SCTP, UDP or other session oriented protocol on an IP network.

21. The server of claim 20 wherein said processor is programmable and operates on data packets transmitted, encapsulated or encoded using an iSCSI, iFCP, infiniband, SATA, SAS, IP, ICMP, IPSEC, DES, 3DES, AES, FC, SCSI, FCIP, NFS, CIFS, DAFS, HTTP, XML, XML derivative, SGML, or HTML format or a combination of any of the foregoing.

22. The server of claim 21 wherein said processor is programmable and operates on data packets transmitted, encapsulated or encoded using an iSCSI, iFCP, infiniband, SATA, SAS, IP, ICMP, IPSEC, DES, 3DES, AES, FC, SCSI, FCIP, NFS, CIFS, DAFS, HTTP, XML, XML derivative, SGML, or HTML format or a combination of any of the foregoing.

23. A storage controller for controlling storage and retrieval to and from a storage area network, of data transmitted over IP networks, said storage controller including a hardware processor providing a TCP/IP protocol termination and origination capability for enabling storage using TCP, SCTP or UDP over IP.

24. The storage controller of claim 23 wherein said hardware processor is included as a companion processor on a chipset of said storage controller.

25. The storage controller of claim 23 wherein said processor is programmable and operates on data packets transmitted, encapsulated or encoded using an iSCSI, iFCP, infiniband, SATA, SAS, IP, ICMP, IPSEC, DES, 3DES, AES, FC, SCSI, FCIP, NFS, CIFS, DAFS, HTTP, XML, XML derivative, SGML, or HTML format or a combination of any of the foregoing.

26. The storage controller of claim 24 wherein said processor is programmable and operates on data packets transmitted, encapsulated or encoded using an iSCSI, iFCP, infiniband, SATA, SAS, IP, ICMP, IPSEC, DES, 3DES, AES, FC, SCSI, FCIP, NFS, CIFS, DAFS, HTTP, XML, XML derivative, SGML, or HTML format or a combination of any of the foregoing.

27. The combination of claim 23 wherein said processor (1) is embedded on a chipset on the storage controller'"'"'s motherboard, or (2) includes the function of data packet security, or (3) includes the function of data packet scheduling, or (3) includes the function of data packet classification.

39. The combination of claim 23 wherein said hardware processor itself includes a processor for performing deep packet inspection and classification.

40. The combination of claim 39 wherein said hardware processor itself includes a processor for performing policy management or policy enforcement on a packet-by-packet basis or per flow or per command or any combination of the foregoing.

28. An IP storage area network switching system line card having embedded therein a hardware processor providing TCP/IP protocol termination and origination capability for enabling high-speed storage using TCP, SCTP or UDP over IP networks, said processor being programmable and operating on data packets transmitted, encapsulated or encoded using an iSCSI, iFCP, infiniband, SATA, SAS, IP, ICMP, IPSEC, DES, 3DES, AES, FC, SCSI, FCIP, NFS, CIFS, DAFS, HTTP, XML, XML derivative, SGML, or HTML format or a combination of any of the foregoing.

35. The combination of claim 28 wherein said hardware processor itself includes a processor for performing deep packet inspection and classification.

36. The combination of claim 35 wherein said hardware processor itself includes a processor for performing policy management or policy enforcement on a packet-by-packet basis or per flow or per command or any combination of the foregoing.

29. A gateway controller of a storage area network, said gateway controller including a chipset having embedded therein a hardware processor providing a TCP/IP protocol termination and origination capability for enabling high-speed storage using TCP, SCTP or UDP over IP networks.

30. The combination of claim 29 wherein said hardware processor is programmable and operates on data packets transmitted, encapsulated or encoded using an iSCSI, iFCP, infiniband, SATA, SAS, IP, ICMP, IPSEC, DES, 3DES, AES, FC, SCSI, FCIP, NFS, CIFS, DAFS, HTTP, XML, XML derivatives, SGML, or HTML format or a combination of any of the foregoing.

31. A storage area network management appliance including a chipset having embedded therein a hardware processor providing a TCP/IP protocol termination and origination capability for enabling transporting storage traffic using TCP, SCTP or UDP over IP networks, said hardware processor enabling said appliance to transport TCP/IP packets in-band to said traffic or out of band to said traffic.

37. The combination of claim 31 wherein said hardware processor itself includes a processor for performing deep packet inspection and classification.

38. The combination of claim 37 wherein said hardware processor itself includes a processor for performing policy management or policy enforcement on a packet-by-packet basis or per flow or per command or any combination of the foregoing.

41. A network comprising one or more system, wherein said one or more system is a server, a host bus adapter, a switch, a switch line card, a gateway, a line card of a gateway, a storage area network appliance, a line card of an appliance, a storage system or a line card of a storage system or a combination of any of the foregoing, said one or more system comprising a hardware processor for enabling data transfer using TCP or other session oriented protocols over IP networks, said processor being programmable and comprising a deep packet classification and/or policy processing engine, used by the said system to enable end to end network management for storage and/or non-storage data networks, said processor applying policies on a per packet, per flow, per command basis, or a combination of per packet, or per flow, or per command basis.