Packet data service over hyper transport link(s)

• US 20040037313A1
• Filed: 01/31/2003
• Published: 02/26/2004
• Est. Priority Date: 05/15/2002
• Status: Active Grant

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Gulati, Manu, Moll, Laurent, Sano, Barton
• Granted Patent: US 7,609,718 B2
• Time in Patent Office: Days
• US Class Current: 370/465
• CPC Class Codes: H04L 12/56 Packet switching systems

Abstract

A multiple processor device generates a control packet for at least one connectionless-based packet in partial accordance with a control packet format of the connection-based point-to-point link and partially not in accordance with the control packet format. For instance, the multiple processor device generates the control packet to include, in noncompliance with the control packet format, one or more of an indication that at least one connectionless-based packet is being transported, an indication of a virtual channel of a plurality of virtual channels associated with the at least one connectionless-based packet, an indication of an amount of data included in the associated data packet, status of the at least one connectionless-based packet, and an error status indication. The multiple processor device then generates the associated data packet in accordance with a data packet format of the connection-based point-to-point link, wherein the data packet includes at least a portion of the at least one connectionless-based packet.

Claims

1. A method for providing connectionless-based packets over a connection based point-to-point link, the method comprises:

generating a control packet in partial accordance with a control packet format of the connection-based point-to-point link, wherein the control packet includes, in noncompliance with the control packet format, an indication that at least one connectionless-based packet is being transported; and

generating a data packet in accordance with a data packet format of the connection-based point-to-point link, wherein the data packet includes at least a portion of the at least one connectionless-based packet, and wherein the data packet is associated with the control packet.

2. The method of claim 1, wherein the generating the control packet further comprises at least one of:

providing an indication of a virtual channel of a plurality of virtual channels associated with the at least one connectionless-based packet;

identifying a source of at least one of the control packet and the data packet;

identifying a destination of at least one of the control packet and the data packet;

providing an indication of an amount of data included in the data packet;

providing status of the at least one connectionless-based packet; and

providing an error status indication.

3. The method of claim 2, wherein the status of the at least one connectionless-based packet further comprises:

a start of packet indication for the at least one connectionless-based packet;

an end of packet indication for the at least one connectionless-based packet;

a middle of packet indication for the at least one connectionless-based packet; and

an indication of a number of valid bytes in a data packet associated with a control packet that includes the end of packet indication.

4. The method of claim 1, wherein the connection-based point-to-point link further comprises a HyperTransport (HT) link.

5. The method of claim 4, wherein the generating the control packet further comprises:

generating a write command in partial accordance with a write command format of the HT link, wherein a portion of an address section of the write command format includes a unique address that indicates that the at least one connectionless-based packet is being transported, such that when a device that is not packet over HT aware forwards the control packet and the data packet in accordance with an HT link protocol and such that when a device is packet over HT aware processes the control packet and data packet.

6. The method of claim 5, wherein the generating the control packet further comprises:

generating a sequence identification field within the control packet to indicate an identity of a virtual channel of a plurality of virtual channels associated with the at least one connectionless-based packet.

7. The method of claim 5, wherein the generating the control packet further comprises:

generating a second portion of the address section to indicate status of the at least one connectionless-based packet.

8. The method of claim 7, wherein the status of the at least one connectionless-based packet further comprises:

a start of packet indication for the at least one connectionless-based packet;

an end of packet indication for the at least one connectionless-based packet;

a middle of packet indication for the at least one connectionless-based packet; and

an indication of a number of valid bytes in a data packet associated with a control packet that includes the end of packet indication.

9. The method of claim 4 further comprises:

generating at least one flow control packet to release at least one buffer for at least one of a plurality of virtual channels.

10. The method of claim 1 further comprises:

determining whether each device in a path to each destination of at least one of control packet and data packet is packet over connection-based link aware;

when each device in a path to each destination is packet over connection-based link aware, directly routing the at least one control packet and data packet to the each destination; and

when at least one device in at least one path is not packet over connection-based link aware, routing the at least one control packet and data packet around the at least one device in the at least one path.

11. A method for processing connectionless-based packets over a connection based point-to-point link, the method comprises:

receiving a packet;

determining whether the packet includes data corresponding to at least one connectionless-based packet based on a noncompliant indication with a standard packet format of the packet; and

when the packet includes the data corresponding to the at least one connectionless-based packet, processing the packet as a connectionless-based packet.

12. The method of claim 11, wherein the determining whether the packet includes data corresponding to the at least one connectionless-based packet further comprises:

interpreting an address portion of the packet to determine whether the address portion contains a unique address that indicates that the at least one connectionless-based packet is being transported.

13. The method of claim 11, wherein the processing the packet further comprises:

determining routing information by at least one of hashing function, random distribution operation, field examination, packet content comparison, and logic function.

14. The method of claim 13, wherein the determining the routing information further comprises:

determining a many-to-many mapping of a plurality of input virtual channels to a plurality of output virtual channels based on at least one of an input virtual channel basis or an output virtual channel basis, wherein the input virtual channel basis utilizes identify of at least one of the plurality of input virtual channels to identify at least one of the plurality of output virtual channels, and wherein the output virtual channel basis uses identity of an output virtual channel of the plurality of output virtual channels to route the packet to an appropriate output buffer.

15. An apparatus for providing connectionless-based packets over a connection based point-to-point link, the apparatus comprises:

processing module; and

memory operably coupled to the processing module, wherein the memory includes operational instructions that cause the processing module to;

generate a control packet in partial accordance with a control packet format of the connection-based point-to-point link, wherein the control packet includes, in noncompliance with the control packet format, an indication that at least one connectionless-based packet is being transported; and

generate a data packet in accordance with a data packet format of the connection-based point-to-point link, wherein the data packet includes at least a portion of the at least one connectionless-based packet, and wherein the data packet is associated with the control packet.

16. The apparatus of claim 15, wherein the memory further comprises operational instructions that cause the processing module to generate the control packet by at least one of:

providing an indication of a virtual channel of a plurality of virtual channels associated with the at least one connectionless-based packet;

identifying a source of at least one of the control packet and the data packet;

identifying a destination of at least one of the control packet and the data packet;

providing an indication of an amount of data included in the data packet;

providing status of the at least one connectionless-based packet; and

providing an error status indication.

17. The apparatus of claim 16, wherein the status of the at least one connectionless-based packet further comprises:

a start of packet indication for the at least one connectionless-based packet;

an end of packet indication for the at least one connectionless-based packet;

a middle of packet indication for the at least one connectionless-based packet; and

an indication of a number of valid bytes in a data packet associated with a control packet that includes the end of packet indication.

18. The apparatus of claim 15, wherein the connection-based point-to-point link further comprises a HyperTransport (HT) link.

19. The apparatus of claim 18, wherein the memory further comprises operational instructions that cause the processing module to generate the control packet by:

generating a write command in partial accordance with a write command format of the HT link, wherein a portion of an address section of the write command format includes a unique address that indicates that the at least one connectionless-based packet is being transported, such that when a device that is not packet over HT aware forwards the control packet and the data packet in accordance with an HT link protocol and such that when a device is packet over HT aware processes the control packet and data packet.

20. The apparatus of claim 19, wherein the memory further comprises operational instructions that cause the processing module to generate the control packet by:

generating a sequence identification field within the control packet to indicate an identity of a virtual channel of a plurality of virtual channels associated with the at least one connectionless-based packet.

21. The apparatus of claim 18, wherein the memory further comprises operational instructions that cause the processing module to generate the control packet by:

generating a second portion of the address section to indicate status of the at least one connectionless-based packet.

22. The apparatus of claim 21, wherein the status of the at least one connectionless-based packet further comprises:

a start of packet indication for the at least one connectionless-based packet;

an end of packet indication for the at least one connectionless-based packet;

a middle of packet indication for the at least one connectionless-based packet; and

an indication of a number of valid bytes in a data packet associated with a control packet that includes the end of packet indication.

23. The apparatus of claim 18, wherein the memory further comprises operational instructions that cause the processing module to:

generate at least one flow control packet to release at least one buffer for at least one of a plurality of virtual channels.

24. The apparatus of claim 15, wherein the memory further comprises operational instructions that cause the processing module to:

determine whether each device in a path to each destination of at least one of control packet and data packet is packet over connection-based link aware;

when each device in a path to each destination is packet over connection-based link aware, directly route the at least one control packet and data packet to the each destination; and

when at least one device in at least one path is not packet over connection-based link aware, route the at least one control packet and data packet around the at least one device in the at least one path.

25. An apparatus for processing connectionless-based packets over a connection based point-to-point link, the apparatus comprises:

processing module; and

memory operably coupled to the processing module, wherein the memory includes operational instructions that cause the processing module to;

receive a packet;

determine whether the packet includes data corresponding to at least one connectionless-based packet based on a noncompliant indication with a standard packet format of the packet; and

when the packet includes the data corresponding to the at least one connectionless-based packet, process the packet as a connectionless-based packet.

26. The apparatus of claim 25, wherein the memory further comprises operational instructions that cause the processing module to determine whether the packet includes data corresponding to the at least one connectionless-based packet by:

interpreting an address portion of the packet to determine whether the address portion contains a unique address that indicates that the at least one connectionless-based packet is being transported.

27. The apparatus of claim 25, wherein the memory further comprises operational instructions that cause the processing module to process the packet by:

determining routing information by at least one of hashing function, random distribution operation, field examination, packet content comparison, and logic function.

28. The apparatus of claim 27, wherein the memory further comprises operational instructions that cause the processing module to determine the routing information by:

determining a many-to-many mapping of a plurality of input virtual channels to a plurality of output virtual channels based on at least one of an input virtual channel basis or an output virtual channel basis, wherein the input virtual channel basis utilizes identify of at least one of the plurality of input virtual channels to identify at least one of the plurality of output virtual channels, and wherein the output virtual channel basis uses identity of an output virtual channel of the plurality of output virtual channels to route the packet to an appropriate output buffer.

29. A multiple processor integrated circuit comprises:

a plurality of processing units;

cache memory;

memory controller operably coupled to system memory;

internal bus operably coupled to the plurality of processing units, the cache memory and the memory controller;

packet manager operably coupled to the internal bus;

node controller operably coupled to the internal bus;

first configurable packet-based interface;

second configurable packet-based interface; and

switching module operably coupled to the packet manager, the node controller, the first configurable packet-based interface, and the second configurable packet-based interface, wherein each of the first and second configurable packet-based interfaces includes;

processing module; and

memory operably coupled to the processing module, wherein the memory includes operational instructions that cause the processing module to;

generate a control packet in partial accordance with a control packet format of the connection-based point-to-point link, wherein the control packet includes, in noncompliance with the control packet format, an indication that at least one connectionless-based packet is being transported; and

generate a data packet in accordance with a data packet format of the connection-based point-to-point link, wherein the data packet includes at least a portion of the at least one connectionless-based packet, and wherein the data packet is associated with the control packet.

30. The multiple processor integrated circuit of claim 29, wherein the memory further comprises operational instructions that cause the processing module to generate the control packet by at least one of:

providing an indication of a virtual channel of a plurality of virtual channels associated with the at least one connectionless-based packet;

identifying a source of at least one of the control packet and the data packet;

identifying a destination of at least one of the control packet and the data packet;

providing an indication of an amount of data included in the data packet;

providing status of the at least one connectionless-based packet; and

providing an error status indication.

31. The multiple processor integrated circuit of claim 30, wherein the status of the at least one connectionless-based packet further comprises:

a start of packet indication for the at least one connectionless-based packet;

an end of packet indication for the at least one connectionless-based packet;

a middle of packet indication for the at least one connectionless-based packet; and

an indication of a number of valid bytes in a data packet associated with a control packet that includes the end of packet indication.

32. The multiple processor integrated circuit of claim 29, wherein the connection-based point-to-point link further comprises a HyperTransport (HT) link.

33. The multiple processor integrated circuit of claim 32, wherein the memory further comprises operational instructions that cause the processing module to generate the control packet by:

generating a write command in partial accordance with a write command format of the HT link, wherein a portion of an address section of the write command format includes a unique address that indicates that the at least one connectionless-based packet is being transported, such that when a device that is not packet over HT aware forwards the control packet and the data packet in accordance with an HT link protocol and such that when a device is packet over HT aware processes the control packet and data packet.

34. The multiple processor integrated circuit of claim 33, wherein the memory further comprises operational instructions that cause the processing module to generate the control packet by:

generating a sequence identification field within the control packet to indicate an identity of a virtual channel of a plurality of virtual channels associated with the at least one connectionless-based packet.

35. The multiple processor integrated circuit of claim 33, wherein the memory further comprises operational instructions that cause the processing module to generate the control packet by:

generating a second portion of the address section to indicate status of the at least one connectionless-based packet.

36. The multiple processor integrated circuit of claim 35, wherein the status of the at least one connectionless-based packet further comprises:

a start of packet indication for the at least one connectionless-based packet;

an end of packet indication for the at least one connectionless-based packet;

a middle of packet indication for the at least one connectionless-based packet; and

an indication of a number of valid bytes in a data packet associated with a control packet that includes the end of packet indication.

37. The multiple processor integrated circuit of claim 29, wherein the memory further comprises operational instructions that cause the processing module to:

generate at least one flow control packet to release at least one buffer for at least one of a plurality of virtual channels.

38. The multiple processor integrated circuit of claim 29, wherein the memory further comprises operational instructions that cause the processing module to:

determine whether each device in a path to each destination of at least one of control packet and data packet is packet over connection-based link aware;

when each device in a path to each destination is packet over connection-based link aware, directly route the at least one control packet and data packet to the each destination; and

when at least one device in at least one path is not packet over connection-based link aware, route the at least one control packet and data packet around the at least one device in the at least one path.

39. The multiple processor integrated circuit of claim 29, wherein the memory further comprises operational instructions that cause the processing module to:

receive a packet;

determine whether the packet includes data corresponding to at least one connectionless-based packet based on a noncompliant indication with a standard packet format of the packet; and

when the packet includes the data corresponding to the at least one connectionless-based packet, process the packet as a connectionless-based packet.

40. The multiple processor integrated circuit of claim 39, wherein the memory further comprises operational instructions that cause the processing module to determine whether the packet includes data corresponding to the at least one connectionless-based packet by:

interpreting an address portion of the packet to determine whether the address portion contains a unique address that indicates that the at least one connectionless-based packet is being transported.

41. The multiple processor integrated circuit of claim 39, wherein the memory further comprises operational instructions that cause the processing module to process the packet by:

determining routing information by at least one of hashing function, random distribution operation, field examination, packet content comparison, and logic function.

42. The multiple processor integrated circuit of claim 41, wherein the memory further comprises operational instructions that cause the processing module to determine the routing information by:

determining a many-to-many mapping of a plurality of input virtual channels to a plurality of output virtual channels based on at least one of an input virtual channel basis or an output virtual channel basis, wherein the input virtual channel basis utilizes identify of at least one of the plurality of input virtual channels to identify at least one of the plurality of output virtual channels, and wherein the output virtual channel basis uses identity of an output virtual channel of the plurality of output virtual channels to route the packet to an appropriate output buffer.