Method and apparatus for multipath signal compensation in spread-spectrum communications systems
First Claim
1. An apparatus comprising:
- a) a compensation circuit adapted to receive input samples from a received multipath signal and compensate the input samples using secondary signal estimates to form compensated samples;
b) a hard-decision circuit adapted to receive the compensated samples and determine a nominal phase value for each input sample, wherein said hard-decision circuit outputs a selected one from a defined set of nominal phase values as the nominal phase value;
c) a buffer circuit adapted to receive the nominal phase value from said hard-decision circuit and maintain a running sequence of past nominal phase values in successive buffer positions corresponding to successively greater sample time offsets with respect to the current input sample;
d) a buffer interface circuit adapted to receive path delay information corresponding to a secondary path signal and provide a selected past nominal phase value, one or more early nominal phase values, and one or more later nominal phase values by retrieving the past nominal phase value currently held in one of said buffer positions corresponding to a sample time offset equal to the received path delay information and further retrieving the one or more early nominal phase values from one or more of said buffer positions which precede said buffer position corresponding to the sample time offset and the one or more later nominal phase values from one or more of said buffer positions which follow said buffer position corresponding to the sample time offset; and
e) an estimation circuit comprising i) memory and calculation logic adapted to receive the selected past nominal phase value selected from said buffer interface circuit, receive and store magnitude and phase information corresponding to the secondary path signal in the received multipath signal, and produce an unscaled secondary signal estimate for a current input sample based on the magnitude and phase information and the past nominal phase value derived from prior input samples;
ii) scaling logic adapted to produce a scaling factor based on the one or more early nominal phase values and the one or more later nominal phase values preceding and following said selected past nominal phase value; and
iii) multiplication logic adapted to combine the unscaled secondary signal estimate and the scaling factor to produce a current secondary signal estimate;
wherein said apparatus is operative to remove secondary path signal interference from the input samples for output as compensated samples to an associated communications system based directly or indirectly upon successive current secondary signal estimates.
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Abstract
The equalizer of the present invention operates on input multipath signal samples, preferably at chip or sub-chip resolution, to remove or substantially cancel the effects of one or more secondary signals from the main path signal. Using predetermined path information for one or more of the secondary path signals, including magnitude, phase, and time offset relative to the main path signal, the equalizer compensates input multipath signal samples by subtracting estimated secondary signal values from the input samples. For each input sample, the equalizer forms a sliced sample, where the sliced sample represents a nominal phase value defined by the modulation scheme used in the original chip or symbol transmission that is closest in value to the actual phase of the input sample. These sliced samples are held in a running buffer and used, in combination with the predetermined path information and scaling logic, to form the estimated secondary signal values for compensating the input samples.
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Citations
39 Claims
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1. An apparatus comprising:
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a) a compensation circuit adapted to receive input samples from a received multipath signal and compensate the input samples using secondary signal estimates to form compensated samples;
b) a hard-decision circuit adapted to receive the compensated samples and determine a nominal phase value for each input sample, wherein said hard-decision circuit outputs a selected one from a defined set of nominal phase values as the nominal phase value;
c) a buffer circuit adapted to receive the nominal phase value from said hard-decision circuit and maintain a running sequence of past nominal phase values in successive buffer positions corresponding to successively greater sample time offsets with respect to the current input sample;
d) a buffer interface circuit adapted to receive path delay information corresponding to a secondary path signal and provide a selected past nominal phase value, one or more early nominal phase values, and one or more later nominal phase values by retrieving the past nominal phase value currently held in one of said buffer positions corresponding to a sample time offset equal to the received path delay information and further retrieving the one or more early nominal phase values from one or more of said buffer positions which precede said buffer position corresponding to the sample time offset and the one or more later nominal phase values from one or more of said buffer positions which follow said buffer position corresponding to the sample time offset; and
e) an estimation circuit comprising i) memory and calculation logic adapted to receive the selected past nominal phase value selected from said buffer interface circuit, receive and store magnitude and phase information corresponding to the secondary path signal in the received multipath signal, and produce an unscaled secondary signal estimate for a current input sample based on the magnitude and phase information and the past nominal phase value derived from prior input samples;
ii) scaling logic adapted to produce a scaling factor based on the one or more early nominal phase values and the one or more later nominal phase values preceding and following said selected past nominal phase value; and
iii) multiplication logic adapted to combine the unscaled secondary signal estimate and the scaling factor to produce a current secondary signal estimate;
wherein said apparatus is operative to remove secondary path signal interference from the input samples for output as compensated samples to an associated communications system based directly or indirectly upon successive current secondary signal estimates. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. An apparatus comprising:
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a) a first compensation circuit adapted to receive input samples from a received multipath signal and compensate input samples using first secondary signal estimates to form first compensated samples;
b) a delay circuit adapted to receive the first compensated samples and output delayed first compensated samples;
c) a second compensation circuit adapted to receive the delayed first compensated samples and compensate the delayed first compensated samples using second secondary signal estimates to form second compensated samples;
d) a hard-decision circuit adapted to receive the compensated input samples and determine a nominal phase value for each first compensated sample, wherein said hard-decision circuit outputs a selected one from a defined set of nominal phase values as the nominal phase value;
e) a buffer circuit adapted to receive the nominal phase value from said hard-decision circuit and maintain a running sequence of past nominal phase values in successive buffer positions corresponding to successively greater sample time offsets with respect to the current input sample based on receiving the nominal phase values output from said hard-decision circuit; and
f) a buffer interface circuit adapted to receive path delay information corresponding to one or more of first and second types of secondary path signals, and further adapted to provide selected past nominal phase values and associated early and later nominal phase values by retrieving the past nominal phase values currently held in said buffer circuit from said buffer positions corresponding to sample time offsets equal to the received path delay information and further retrieving the early nominal phase values currently held in said buffer circuit from said buffer positions which precede said buffer positions corresponding to the sample time offsets and the later nominal phase values currently held in said buffer circuit from said buffer positions which follow said buffer positions corresponding to the sample time offsets;
g) one or more first estimation circuits each adapted to provide a current first secondary signal estimate for the first type of secondary path signal, each of said first estimation circuits comprising;
i) first memory and calculation logic adapted to receive the selected past nominal phase values, receive and store magnitude and phase information corresponding to a secondary path signal of the first type in the received multipath signal, and produce an unscaled first secondary signal estimate for an input sample based on the magnitude and phase information and a one of the selected past nominal phase values derived from prior input samples;
ii) first scaling logic adapted to produce a scaling factor based on one or more early and later nominal phase values preceding and following the one of the selected past nominal phase values; and
iii) first multiplication logic adapted to combine said unscaled first secondary signal estimate with said scaling factor to produce the current first secondary signal estimate; and
h) one or more second estimation circuits each adapted to provide a current second secondary signal estimate for the second type of secondary path signal, each of said second estimation circuits comprising i) second memory and calculation logic adapted to receive the selected past nominal phase values, receive and store magnitude and phase information corresponding to a secondary path signal of the second type in the received multipath signal, and produce an unscaled second secondary signal estimate for an input sample based on the magnitude and phase information and a second one of the selected past nominal phase values derived from prior input samples;
ii) second scaling logic adapted to produce a scaling factor based on one or more early and later nominal phase values preceding and following the second one of the selected past nominal phase values; and
iii) second multiplication logic adapted to combine said unscaled second secondary signal estimate with said scaling factor to produce the current second secondary signal estimate;
wherein said apparatus is operative to remove secondary path signal interference for one or more of the first and second types of secondary path signals based either directly or indirectly upon one or more of the current first and current second secondary signal estimates, further wherein the first type of secondary signal has a path delay greater than a path delay of a main path signal in the received multipath signal and the second type of secondary path signal has a path delay less than the path delay of the main path signal. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32)
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33. An apparatus comprising:
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a) a delay circuit adapted to receive input samples from a received multipath signal and output delayed samples;
b) a compensation circuit adapted to receive the delayed samples and compensate the delayed samples using secondary signal estimates to form compensated samples;
c) a hard-decision circuit adapted to receive the input samples and output a nominal phase value for each input sample;
d) a buffer circuit adapted to receive the nominal phase value from said hard-decision circuit and maintain a running sequence of past nominal phase values in successive buffer positions corresponding to successively greater sample time offsets with respect to the current input sample based on receiving past nominal phase values output from the hard-decision circuit; and
e) a buffer interface circuit adapted to receive path delay information corresponding to the secondary path signal and provide a selected past nominal phase value, one or more early nominal phase values, and one or more later nominal phase values by retrieving the past nominal phase value currently held in one of said buffer positions corresponding to a sample time offset equal to the received path delay information and further retrieving the one or more early nominal phase values from one or more of said buffer positions which precede said buffer position corresponding to the sample time offset and the one or more later nominal phase values from one or more of said buffer positions which follow said buffer position corresponding to the sample time offset; and
g) an estimation circuit comprising i) memory and calculation logic adapted to receive the selected past nominal phase value selected from said buffer interface circuit, receive and store magnitude and phase information corresponding to a secondary path signal in the received multipath signal, and produce an unscaled secondary signal estimate for a current input sample based on the magnitude and phase information and the past nominal phase value derived from prior input samples;
ii) scaling logic adapted to produce a scaling factor based on the one or more early nominal phase values and the one or more later nominal phase values preceding and following said selected past nominal phase value; and
iii) multiplication logic adapted to combine the unscaled secondary signal estimate and the scaling factor to produce a current secondary signal estimate;
wherein said apparatus is operative to remove secondary path signal interference from the received multipath signal due to the secondary path signal based directly or indirectly upon successive current secondary signal estimates. - View Dependent Claims (34, 35, 36, 37, 38, 39)
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Specification