Receivers for controlled frequency signals

• US 20040037382A1
• Filed: 08/21/2002
• Published: 02/26/2004
• Est. Priority Date: 08/21/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Griffin, Jed D., Self, Keith M., Prince, Brett A., Jex, Jerry G.
• Granted Patent: US 7,158,594 B2
• Time in Patent Office: Days
• US Class Current: 375/354
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 25/085 Arrangements for reducing interference in line transmission systems, e.g. by differential transmission
• CPC Class Codes: H04L 25/4908 using mBnB codes

Abstract

In some embodiments, a receiver includes a first conductor to carry a magnitude encoded controlled frequency signal (CFS) and a second conductor to carry a complementary magnitude encoded controlled frequency signal (CCFS). The receiver further includes circuitry to receive the CFS and CCFS from the first and second conductors and to decode them to produce an output signal. Other embodiments are described and claimed.

Claims

1. A chip comprising:

a receiver including;

a first conductor to carry a magnitude encoded controlled frequency signal (CFS) and a second conductor to carry a complementary magnitude encoded controlled frequency signal (CCFS); and

circuitry to receive the CFS and CCFS from the first and second conductors and to decode them to produce an output signal.

2. The chip of claim 1, wherein the output signal is a time delayed version of an input signal used in creating the CFS and CCFS.

3. The chip of claim 1, wherein the output signal is an inverse of a time delayed version of an input signal used in creating the CFS and CCFS.

4. A chip comprising:

a receiver including;

a first conductor to carry a magnitude encoded controlled frequency signal (CFS) and a second conductor to carry a complementary magnitude encoded controlled frequency signal (CCFS);

a magnitude encoded controlled frequency (MECF) decoder circuit coupled to the first and second conductors to receive the CFS and CCFS and to provide in response thereto a asynchronous decoded output signal;

clock deriving circuitry coupled to the first and second conductors to receive the CFS and CCFS and to provide in response thereto a derived clock signal; and

synchronizing circuitry to receive the asynchronous decoded output signal, a system clock and the derived clock signal and to provide a synchronized decoded output signal responsive thereto.

5. The chip of claim 4, wherein the clock deriving circuitry includes a comparator to compare the CFS and CCFS and provide the derived clock signal responsive thereto.

6. The chip of claim 5, wherein the clock deriving circuitry includes an additional comparator to compare the CFS and CCFS and provide an inverse of the derived clock signal responsive thereto and wherein the synchronizing circuitry uses the inverse of the derived clock signal and the derived clock signal to provide the synchronized decoded output signal.

7. The chip of claim 4, wherein the clock deriving circuitry includes:

averaging circuitry to provide an averaged signal of the CFS and CCFS;

reference inverting circuitry to provide a reference inverse of the average signal with respect to a reference voltage; and

a comparator to compare the averaged signal and the reference inverse to produce the derived clock signal.

8. The chip of claim 7, wherein the clock deriving circuitry further includes an additional comparator to compare the averaged signal and the reference inverse to produce an inverse of the derived clock signal.

9. The chip of claim 7, wherein the reference inverter circuitry includes enabling transistors between inverters and power and ground signals.

10. The chip of claim 9, wherein the enabling transistors each have a lower Beta than do transistors of the inverters.

11. The chip of claim 4, wherein the MECF decoder includes a comparator to compare the CFS and CCFS and provide the asynchronous decoded output signal.

12. The chip of claim 4, wherein the MECF decoder includes an additional comparator to compare the CFS and CCFS and provide an inverse of the asynchronous decoded output signal.

13. The chip of claim 4, wherein the asynchronous decoded output signal is a time delayed version of an input signal used in creating the CFS and CCFS.

14. The chip of claim 4, wherein the asynchronous decoded output signal is a logical inverse of a time delayed version of an input signal used in creating the CFS and CCFS.

15. The chip of claim 4, wherein the MECF decoder includes:

averaging circuitry to provide an averaged signal of the CFS and CCFS;

reference inverting circuitry to provide a reference inverse of the average signal with respect to a reference voltage; and

a comparator to compare the averaged signal and the reference inverse to produce the asynchronous decoded output signal.

16. The chip of claim 15, wherein the MECF decoder further includes an additional comparator compare the averaged signal and the reference inverse to produce an inverse of the asynchronous decoded output signal.

17. The chip of claim 15, wherein the reference inverter circuitry includes enabling transistors between inverters and power and ground signals.

18. The chip of claim 15, wherein the enabling transistors each have a lower Beta than do transistors of the inverters.

19. The chip of claim 4, wherein the MECF decoder includes:

first passing circuitry to selectively pass the CFS or CCFS;

second passing circuitry to selectively pass the CFS or CCFS;

a first comparator to compare the passed CFS or CCFS from the first passing circuitry with a high threshold voltage and provide an output responsive thereto;

a second comparator to compare the passed CFS or CCFS from the second passing circuitry with a low threshold voltage and provide an output responsive thereto;

a third comparator to compare the outputs of the first and second comparators to produce the asynchronous decoded output signal.

20. The chip of claim 19, wherein the first and second passing circuitry receives the derived clock signal and an inverse derived clock signal.

21. The chip of claim 4, further comprising first and second electromagnetic receivers to receive first and second electromagnetic signals representing the CFS and CCFS and to convert them to the CFS and CCFS.

22. A system comprising:

a first chip including a transmitter to create a magnitude encoded controlled frequency signal (CFS) and a complementary a magnitude encoded controlled frequency signal (CCFS) responsive to an input signal; and

a second chip including a receiver to receive the CFS and CCFS from the first and second conductors and to decode them to produce an output signal.

23. The system of claim 22, wherein the output signal is a time delayed version of the input signal.

24. The system of claim 22, wherein the output signal is an inverse of a time delayed version of the input signal.

25. The system of claim 22, wherein the transmitter creates the CFS and CCFS responsive to the input signal and an inverse of the input signal.

26. The system of claim 22, wherein the receiver includes:

a first conductor to carry the CFS and a second conductor to carry the CCFS;

a magnitude encoded controlled frequency (MECF) decoder circuit coupled to the first and second conductors to receive the CFS and CCFS and to provide in response thereto a asynchronous decoded output signal;

clock deriving circuitry coupled to the first and second conductors to receive the CFS and CCFS and to provide in response thereto a derived clock signal; and

synchronizing circuitry to receive the asynchronous decoded output signal, a system clock and the derived clock signal and to provide the output signals, which is a synchronized decoded output signal responsive thereto.

27. The system of claim 26, wherein the clock deriving circuitry includes a comparator to compare the CFS and CCFS and provide the derived clock signal responsive thereto.

28. The system of claim 27, wherein the clock deriving circuitry includes an additional comparator to compare the CFS and CCFS and provide an inverse of the derived clock signal responsive thereto and wherein the synchronizing circuitry uses the inverse of the derived clock signal and the derived clock signal to provide the synchronized decoded output signal.

29. The system of claim 26, wherein the clock deriving circuitry includes:

averaging circuitry to provide an averaged signal of the CFS and CCFS;

reference inverting circuitry to provide a reference inverse of the average signal with respect to a reference voltage; and

a comparator to compare the averaged signal and the reference inverse to produce the derived clock signal.

30. The system of claim 29, wherein the clock deriving circuitry further includes an additional comparator to compare the averaged signal and the reference inverse to produce an inverse of the derived clock signal.

31. The system of claim 26, wherein the MECF decoder includes a comparator to compare the CFS and CCFS and provide the asynchronous decoded output signal.

32. The system of claim 26, wherein the MECF decoder includes an additional comparator to compare the CFS and CCFS and provide an inverse of the asynchronous decoded output signal.

33. The system of claim 26, wherein the asynchronous decoded output signal is a time delayed version of an input signal used in creating the CFS and CCFS.

34. The system of claim 26, wherein the asynchronous decoded output signal is a logical inverse of a time delayed version of an input signal used in creating the CFS and CCFS.

35. The system of claim 26, wherein the MECF decoder includes:

first passing circuitry to selectively pass the CFS or CCFS;

second passing circuitry to selectively pass the CFS or CCFS;

a first comparator to compare the passed CFS or CCFS from the first passing circuitry with a high threshold voltage and provide an output responsive thereto;

a second comparator to compare the passed CFS or CCFS from the second passing circuitry with a low threshold voltage and provide an output responsive thereto;

a third comparator to compare the outputs of the first and second comparators to produce the asynchronous decoded output signal.

36. The system of claim 35, wherein the first and second passing circuitry receives the derived clock signal and an inverse derived clock signal.

37. The system of claim 22, further comprising first and second electromagnetic receivers to receive first and second electromagnetic signals representing the CFS and CCFS and to convert them to the CFS and CCFS.