Structure and fabricating method with self-aligned bit line contact to word line in split gate flash

• US 20040038479A1
• Filed: 08/20/2002
• Published: 02/26/2004
• Est. Priority Date: 08/20/2002
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsieh, Chia Ta
• Granted Patent: US 6,858,494 B2
• Time in Patent Office: Days
• US Class Current: 438/257
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A new structure is disclosed for semiconductor devices in which contact regions are self-aligned to conductive lines. Openings to a gate oxide layer, in partially fabricated devices on a silicon substrate, have insulating sidewalls. First polysilicon lines disposed against the insulating sidewalls extend from below the top of the openings to the gate oxide layer. Oxide layers are grown over the top and exposed sides of the first polysilicon lines serving to insulate the first polysilicon lines. Polysilicon contact regions are disposed directly over and connect to silicon substrate regions through openings in the gate oxide layer and fill the available volume of the openings. Second polysilicon lines connect to the contact regions and are disposed over the oxide layers grown on the first polysilicon lines.

Claims

1. A structure for semiconductor devices in which contact regions are self aligned to conductive lines, comprising:

A silicon substrate having thereon partially fabricated devices with openings,

first polysilicon lines disposed against insulating sidewalls of said openings in said partially fabricated devices on a silicon substrate, said first polysilicon lines extending from below the top of the openings to above said silicon substrate;

oxide layers formed over the top and sides of said first polysilicon lines that are not against insulating sidewalls of said openings and serving to insulate the first polysilicon lines;

polysilicon contact regions disposed directly over and connecting to silicon substrate regions and Filling said openings;

second polysilicon lines connecting to said contact regions and disposed over said oxide layers formed on said first polysilicon lines.

2. The structure of claim 1 wherein said partially fabricated devices are split gate flash cells.

3. The structure of claim 1 wherein said insulating sidewalls are sidewalls of oxide regions.

4. The structure of claim 1 wherein said first polysilicon lines are spacers serving as word lines.

5. The structure of claim 1 wherein said oxide layers grown on said first polysilicon lines are greater than about 150 Angstroms thick.

6. The structure of claim 1 wherein said silicon substrate regions connecting to said contact regions are drain regions.

7. The stricture of claim 1 wherein said second polysilicon lines are word lines connecting to drain regions.

21. The structure of claim 1 wherein said isolation regions are shallow trench isolation regions.

8. A method of fabricating a structure for semiconductor devices in which contact regions are self aligned to conductive lines, comprising:

providing partially processed devices on a silicon substrate having openings with insulating sidewalls, said openings extending to a gate oxide layer on the silicon substrate;

forming first polysilicon lines against the insulating side walls, extending from the top of said openings to said gate oxide layer on the silicon substrate;

growing an oxide layer on exposed sides of said first polysilicon lines whose thickness is greater than about three times the thickness of said gate oxide layer;

implanting ions t-rough the gate oxide layer of the openings, that are not covered by said first polysilicon lines, to form device regions in the silicon substrate;

performing an oxide etch sufficient to remove all the gate oxide layer of the openings, that are not covered by said first polysilicon lines, but leaving a thickness of oxide over said polysilicon lines that is greater than the thickness of the gate oxide layer;

forming contact region-s by filling the remaining volume of said openings with polysilicon;

forming second polysilicon lines that are connected to said contact regions.

9. The method of claim 8 wherein said partially fabricated devices are split gate flash cells.

10. The method of claim 8 wherein said insulating sidewalls are sidewalls of oxide regions.

11. The method of claim 8 wherein said first polysilicon lines are spacers serving as word lines.

12. The method claim 8 wherein thickness of said gate oxide layer is greater than about 150 Angstroms.

13. The method of claim 8 wherein said device regions in the silicon substrate are drain regions.

14. The method of claim 9 wherein said second polysilicon lines are word lines connecting to drain regions.

15. The method of claim 8 wherein said first polysilicon lines are formed by depositing a first polysilicon layer, performing CMP on said first polysilicon layer to reduce the layer to the top of said openings and performing a spacer etch back to produce first polysilicon lines, having rectangular cross-sections.

16. The method of claim 8 wherein said implanted ions are As ions implanted at energy of about 60 keV to a dose of about 4E15 per cm2.

17. The method of claim 8 wherein said contact regions and second polysilicon lines are formed by depositing a second polysilicon layer, forming and patterning a photoresist layer and etching said second polysilicon layer.

18. A new structure for split gate flash memories in which contact regions are self aligned to conductive lines, comprising:

a silicon region extending to the surface of a semiconductor wafer with alternating parallel columns of source and drain regions;

rows of device regions that are separated by isolation regions and are perpendicular to the source/drain columns, with polysilicon contact regions disposed over drain regions connecting the drain regions to polysilicon bit lines which mun in the row direction over the device regions, and said device regions as they are situated between consecutive drain regions are, in order of occurrence;

a spacer region, a floating gate region, a source line region, a floating gate region and a spacer region;

spacer regions composed of polysilicon lines, which serve as word lines in the column direction, that have oxide layers that were grown on the sides facing contact regions and on the top facing bit lines and oxide layers separating the spacer regions from the silicon region and from the adjacent floating gate region;

floating gate regions composed of a gate oxide layer over the silicon region that separates the silicon region from a polysilicon floating gate followed by an oxide layer, giving a total height some what greater than the other device regions, and oxide spacers separate the floating gate regions from adjacent source line regions;

source line regions composed of polysilicon lines in the column direction that contact source regions at the surface of the silicon region.

19. The structure of claim 18 wherein said silicon region is p-type silicon.

20. The structure of claim 18 wherein said source and drain regions are n-type silicon regions.

22. The structure of claim 18 wherein said polysilicon contact regions, polysilicon bit lines, polysilicon word lines, polysilicon floating gates and polysilicon source lines are P doped to achieve high conductivity.

23. The structure of claim 18 wherein the grown oxide layers on said polysilicon word lines, on the sides of facing contact regions and on the top facing bit lines, are thicker than about 150 Angstroms.

24. A method of fabricating a new structure for split gate flash memories in which contact regions are self aligned to conductive lines, comprising:

providing a silicon substrate and forming parallel alternating isolation regions and active regions;

forming a gate oxide-1 layer over said active regions;

forming a doped poly-1 layer over said gate oxide-1 layer;

forming a silicon nitride layer over said poly-1 layer;

forming and patterning a first photoresist layer and etching said silicon nitride layer to form equally spaced parallel, alternating wide and narrow silicon nitride sections perpendicular to the active regions;

etching said poly-1 layer between said silicon nitride sections to form sloped poly-1 profiles;

removing said first photoresist layer;

depositing an oxide-2 layer and performing CMP on this layer to the level of the silicon nitride sections;

forming and patterning a second photoresist layer and sequentially etching the narrow silicon nitride sections and the underlying poly-1 regions to expose the underlying gate oxide-1 and creating narrow openings;

performing a source ion implantation to form source regions under the exposed gate oxide-1;

removing the second photoresist layer;

forming an oxide-3 layer and etching said oxide-3 layer to form oxide-3 spacers along d sidewalls;

depositing a doped poly-2 layer and performing CMP to remove all poly-2 outside said narrow openings and creating poly-2 source lines running perpendicular to the active regions and contacting the source regions;

forming oxide-4 caps over the tops of said poly-2 source lines;

performing a silicon nitride etch to remove the wide silicon nitride sections and creating wide openings;

sequentially etching the poly-2 layer and oxide-layer from the bottoms of the wide openings;

forming an oxide-5 layer over exposed silicon and polysilicon surfaces;

forming a doped poly-3 layer- and perform CMP on said poly-3 layer to the top of the oxide-2 layer;

performing a poly-3 etch to form poly-3 spacer regions that act as word lines running perpendicular to the active regions;

forming an oxide-6 layer over exposed surfaces of poly-3 spacer regions;

performing a drain ion implantation to form drain regions under the exposed oxide-5;

performing an oxide etch to remove exposed oxide-5 and underlying oxide formed during formation of said oxide-6 layer but leaving an oxide-6 layer of reduced thickness over said poly-3 spacer regions;

forming a doped poly-4 layer;

forming and patterning a third photoresist layer and etching said poly-4 layer to produce poly-4 lines over said active regions that serve as bit lines.

25. The method of claim 24 wherein said isolation regions are shallow trench isolation regions.

26. The method of claim 24 wherein said silicon substrate is a p-type silicon substrate.

27. The method of claim 24 wherein said gate oxide-1 layer is formed by growing an oxide to a thickness of about 90 Angstroms.

28. The method of claim 24 wherein said poly-1 layer is formed to a thickness of about 800 Angstroms.

29. The method of claim 24 wherein said poly-1 layer is doped with phosphorus, either in situ or by ion implantation, to achieve high conductivity.

30. The method of claim 24 wherein said silicon nitride layer is formed to a thickness of about 2500 Angstroms.

31. The method of claim 24 wherein said oxide-2 layer is deposited to a thickness of about 2000 Angstroms.

32. The method of claim 24 wherein said source ion implantation is performed with P ions at energy of about 20 keV to a dose of about 4E14 per cm2.

33. The method of claim 24 wherein said oxide-3 layer is deposited to a thickness of about 250 Angstroms.

34. The method of claim 24 wherein said poly-2 layer is formed to a thickness of about 800 Angstroms.

35. The method of claim 24 wherein said poly-2 layer is doped with phosphorus either in situ or by ion implantation, to achieve high conductivity.

36. The method of claim 24 wherein said oxide-4 caps are formed by growing oxide layers on the tops of said poly-2 source lines to a thickness of about 200 Angstroms.

37. The method of claim 24 wherein said oxide-5 layer is grown to a thickness of about 170 Angstroms over silicon surfaces.

38. The method of claim 24 wherein said poly-3 layer is formed to a thickness of about 2000 Angstroms.

39. The method of claim 24 wherein said poly-3 layer is doped with phosphorus, either in situ or by ion implantation, to achieve high conductivity.

40. The method of claim 24 wherein said oxide-6 layer is formed by growing an oxide layer to a depth of about 600 Angstroms over said exposed surfaces of poly-3 spacers.

41. The method of claim 24 wherein said drain ion implantation is performed with As ions at energy of about 60 keV to a dose of about 4E15 per cm2.

42. The method of claim 24 wherein said poly-4 layer is formed to a thickness of about 2000 Angstroms.

43. The method of claim 24 wherein said poly-4 layer is doped with phosphorus, either in situ or by ion implantation, to achieve high conductivity.