TRENCH ETCH PROCESS FOR LOW-K DIELECTRICS

• US 20040038540A1
• Filed: 10/05/2001
• Published: 02/26/2004
• Est. Priority Date: 10/05/2001
• Status: Active Grant

• Current Assignee: Lam Research Corporation
• Original Assignee: Lam Research Corporation
• Inventors: Kang, Sean, Cirigliano, Peter, Pohray, Vinay, Sadjadi, S.M. Reza, Pirkle, David R., Li, SiYi, Lassig, Stephan
• Granted Patent: US 6,794,293 B2
• Time in Patent Office: Days
• US Class Current: 438/700
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/312 Organic layers, e.g. photoresist H01L21/3105, H01L21/32 take precedence; photoresists per se G03C
• CPC Class Codes: H01L 21/3124 layers comprising hydrogen silsesquioxane
• CPC Class Codes: H01L 21/3127 Layers comprising fluoro (hydro)carbon compounds, e.g. polytetrafluoroethylene
• CPC Class Codes: H01L 21/31629 Deposition of halogen doped silicon oxide, e.g. fluorine doped silicon oxide
• CPC Class Codes: H01L 21/31695 Deposition of porous oxides or porous glassy oxides or oxide based porous glass
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material

Abstract

The present inventions is a method of trench formation within a dielectric layer, comprising, first, etching a via within the dielectric layer. After the via is etched, an organic plug is used to fill a portion of the via. After the desired amount of organic plug has been etched from the via, a trench is etched with a first gas mixture to a first depth, and a second gas mixture is used to further etch the trench to the final desired trench depth. Preferably, the method is used for low-k dielectrics that do not have an intermediate etch stop layer. Additionally, it is preferable that the first gas mixture is a polymeric gas mixture and the second gas mixture is a non-polymeric gas mixture. As a result of using this method, an interconnect structure for a low-k dielectric without an intermediate etch stop layer having a trench with trench edges that are substantially orthogonal and a via with via edges that are substantially orthogonal is generated.

Claims

1. A method of trench formation within a dielectric layer, comprising:

first, etching a via within said dielectric layer, said via having a first depth;

second, depositing an organic plug layer within said via;

third, etching a trench with a first gas mixture to a second depth, said second depth being less than said first depth; and

fourth, further etching said trench with a second gas mixture to a third depth, said third depth being greater than said second depth and less than said first depth.

2. The method of claim 1 further comprising providing an intermediate layer between said via and said trench, said intermediate layer being at said third depth.

3. The method of claim 1 wherein said dielectric layer has a metallized object beneath the dielectric layer separated by a barrier layer, the method including a fifth etching step of etching through said barrier layer to the metallized object.

4. The method of claim 1 applied to the formation of a via-first dual damascene structure on a wafer further comprising, depositing a hardmask on said dielectric prior to etching a via within said dielectric layer that identifies identifies the location of said via with said hardmask.

5. The method of claim 1 wherein said dielectric layer is a low-k material having a k value of less than 3.0.

6. The method of claim 5 wherein said dielectric layer is an organosilicate glass dielectric.

7. The method of claim 1 wherein said first gas mixture is a polymerized gas mixture.

8. The method of claim 7 wherein said polymerized gas mixture includes a fluoro-carbon gas.

9. The method of claim 7 wherein said polymerized gas mixture includes a hydro-fluoro-carbon gas.

10. The method of claim 7 wherein said second gas mixture is a non-polymerized gas mixture.

11. The method of claim 10 wherein said non-polymerized gas mixture includes NF₃.

12. The method of claim 10 wherein said non-polymerized gas mixture include CF₄.

13. A method of trench formation within a low-k dielectric layer without an intermediate etch-stop layer, comprising:

first, etching a via within said dielectric layer, said via having a first depth;

second, etching a trench with a first gas mixture to a second depth, said second depth being less than said first depth; and

third, etching said trench with a second gas mixture to a third depth, said third depth being greater than said second depth and less than said first depth.

14. The method of claim 13 wherein said first gas mixture is a polymerized gas mixture.

15. The method of claim 14 wherein said second gas mixture is a non-polymerized gas mixture.

16. The method of claim 15 wherein said low-k dielectric layer has a k value of less than 3.0.

17. The method of claim 15 wherein said low-k dielectric layer is an organosilicate glass dielectric.

18. The method of claim 15 wherein said low-k dielectric layer has a metallized object beneath said low-k dielectric layer separated by a barrier layer, the method including a fifth etching step of etching through said barrier layer to said metallized object.

19. The method of claim 15 applied to the formation of a via-first dual damascene structure on a wafer further comprising, depositing a hardmask on said low-k dielectric prior to etching a via within said low-k dielectric layer that identifies the location of the said via with said hardmask.

20. An interconnect structure, comprising:

a low-k dielectric without an intermediate etch-stop layer;

a trench having a plurality of trench edges, said plurality of trench edges having a substantially orthogonal shape, said trench having a first width and a first depth within said low-k dielectric;

a via beneath said trench and within said low-k dielectric, said via having a plurality of via edges, said plurality of via edges having a substantially orthogonal shape, said via having a second width and a second depth, said second width being smaller than said trench first width and second depth being greater than said trench first depth.

21. The interconnect structure of claim 20 further comprising a terrace between said trench and said via, said terrace having a third width that is greater than said second via width.

22. The interconnect structure of claim 20 further comprising a metallized object beneath said via.

23. The interconnect structure of claim 21 further comprising a metallized object beneath said via.

24. The interconnect structure of claim 20 wherein said interconnect structure is a dual damascene structure.