High dynamic range cascaded integration pixel cell and method of operation

• US 20040041077A1
• Filed: 08/29/2002
• Published: 03/04/2004
• Est. Priority Date: 08/29/2002
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Micron Technology, Inc.
• Inventors: Fossum, Eric R.
• Granted Patent: US 6,888,122 B2
• Time in Patent Office: Days
• US Class Current: 250/208.1
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H04N 25/59 by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

A cascaded imaging storage system for a pixel is disclosed for improving intrascene dynamic range. Charges accumulated in a first capacitor spill over into a second capacitor when a charge storage capacity of the first capacitor is exceeded. A third capacitor may also be provided such that charges accumulated by said second capacitor spill over into the third capacitor when the charge storage capacity of the second capacitor is exceeded.

Claims

1. An imager pixel cell comprising:

a semiconductor device for converting light energy into electrical charges during an integration period;

a first capacitor associated with said device for accumulating charge converted by said device during said integration period;

at least one other capacitor for accumulating charge converted by said device when said converted charge exceeds a first threshold value during said integration period; and

a readout circuit for reading out the voltage accumulated by said first and said at least one other capacitor at the end of said integration period.

2. An imager pixel cell as in claim 1 wherein said at least one other capacitor comprises a second capacitor and a third capacitor, said second capacitor accumulating charge when said converted charge exceeds said first threshold, said third capacitor accumulating charge when said converted charge exceeds a second threshold.

3. An imager cell as in claim 2 further comprising a reset device for resetting the voltage on said semiconductor device and first capacitor to a predetermined value prior to said integration period, said reset device being operative when said converted charge exceeds a threshold to prevent converted charge from being accumulated by any of said capacitors.

4. An imager pixel cell as in claim 1 wherein said first capacitor is a parasitic capacitance associated with said semiconductor device.

5. An imager pixel cell as in claim 1 wherein said first capacitor is a discrete capacitor connected to said semiconductor device.

6. An imager pixel cell as in claim 1 wherein said at least one other capacitor has a capacitance value greater that said first capacitor and said third capacitor has a capacitance value greater than said second capacitor.

7. An imager pixel cell as in claim 2 wherein said second capacitor has a capacitance value greater than said first capacitor and said third capacitor has a capacitance value greater than said second capacitor.

8. A imager pixel cell as in claim 1 wherein said readout circuit first reads out voltage from said first capacitor and then reads out voltage from said first and said at least one other capacitor.

9. An imager pixel cell as in claim 2 wherein said readout circuit first reads out voltage from said first capacitor, then reads out voltage from said first and second capacitors, and then reads out voltage from said first, second and third capacitors.

10. An imager pixel cell comprising:

a semiconductor conversion device for generating electrical charges in response to photon energy impinging thereon;

a first reset transistor for resetting said conversion device to a predetermined voltage during a reset period;

a storage system for storing said electrical charges, said storage system comprising a sequence of capacitors arranged such that a later capacitor in a sequence stores charge which overflows from an earlier capacitor in said sequence during an integration period; and

a pixel cell readout circuit for reading out voltage stored in said storage system to an output line.

11. An imager pixel cell as in claim 10 wherein said sequence of capacitors comprises a first and second capacitor.

12. An imager pixel cell as in claim 10 wherein said sequence of capacitors comprises a first, second and third capacitor.

13. An imager pixel cell as in claim 10 wherein said sequence of capacitors stores charge in a sequential fashion.

17. An imager pixel cell as in claim 12 wherein said second capacitor is connected to said conversion device through a second transfer transistor and said third capacitor is connected to said conversion device through a third transfer transistor.

18. An imager pixel cell as in claim 17 wherein said second transistor directly couples said second capacitor to said conversion device.

19. An imager pixel cell as in claim 17 wherein said third transistor directly couples said third capacitor to said conversion device.

20. An imager pixel as in claim 17 wherein said third transistor couples said third capacitor to said conversion device through said second transistor.

21. An imager pixel cell as in claim 17 wherein said second and third transistors respectively set barrier potentials which must be exceeded before said second and third capacitors respectively begin to storage charges.

22. An imager pixel cell as in claim 21 wherein said barrier potentials are adjustable by gate voltages applied to said second and third transistors.

23. An imager pixel cell as in claim 22 wherein the barrier potentials set by said second and third transistor switches are the same.

24. An imager pixel cell as in claim 22 wherein the barrier potentials set by said second and third transistors are different.

25. An imager pixel as in claim 10 wherein said first reset transistor is arranged to apply a reset voltage directly to said conversion device.

26. An imager pixel cell as in claim 17 wherein said first reset transistor is arranged to apply said reset voltage directly to said conversion device.

27. An imager pixel cell as in claim 17 wherein said first reset transistor is arranged to apply said reset voltage to said conversion device through said second and third transistors.

28. An imager pixel cell as in claim 10 wherein said readout circuit first reads out voltage from a first capacitor in said sequence and thereafter reads out voltage from said first capacitor and at least one other capacitor in said sequence.

29. An imager pixel cell as in claim 11 wherein said first capacitor is sequentially before said second capacitor and wherein said readout circuit first reads out voltage from said first capacitor and thereafter reads out voltage from said first and second capacitors.

30. An imager pixel cell as in claim 12 wherein said first capacitor is sequentially before said second capacitor and said second capacitor is sequentially before said third capacitor, and wherein said readout circuit first reads out voltage from said first capacitor, then reads out voltage from said first and second capacitors.

14. An imager pixel cell as in 10 wherein said storage system further comprises a transfer transistor for controlling charge transfer from an earlier capacitor to a later capacitor in said sequence and wherein the flow of charge from a said earlier capacitor to said later capacitor is determined by a barrier potential set by said transfer transistor.

15. An imager pixel as in claim 14 wherein said barrier potential is variable in accordance with a gate voltage applied to said transfer transistor.

16. An imager pixel cell as in claim 14 wherein a first of said capacitors in said sequence receives and stores charges directly from said conversion device, while a later capacitor in the sequence receives charges from said conversion device through said transfer transistor.

31. An imager pixel cell comprising:

a photodiode for generating electrical charges in response to photons impinging thereon;

a first switch for resetting a node of said photodiode to a reset voltage prior to an integration period;

a first capacitor connected to said node for accumulating charge during a pixel integration period;

a second capacitor connectable to said node by a second switch; and

a readout circuit for reading out a signal from said node upon completion of said integration period.

32. An imager pixel cell as in claim 31 further comprising a third capacitor connectable to said node by a third switch.

33. An imager pixel as in claim 31 wherein said readout circuit comprises a source follower transistor having a gate connected to said node and a select transistor which couples an output signal of said source follower transistor to an output line in response to a selection signal applied to the gate of said select transistor.

34. A pixel cell as in claim 31 wherein said second switch is operable to selectively connect said second capacitor to said node to accumulate charge during at least a portion of said integration period.

35. An imager pixel as in claim 32 wherein said third switch is operable to selectively connect said third capacitor to said node so that said third capacitor accumulates charge during at least a portion of said integration period.

36. An imager pixel cell as in claim 34 wherein said second switch is operable to connect said second capacitor to said node throughout said integration period.

37. An imager pixel cell as in claim 34 wherein said second switch is operable to connect said capacitor to said node a first predetermined time after said integration period begins.

38. An imager pixel cell as in claim 35 wherein said third switch is operable to connect said third capacitor to said node throughout said integration period.

39. An imager pixel cell as in claim 35 wherein said third switch is operable to connect said third capacitor to said node a predetermined time after said integration period begins.

40. An imager pixel as in claim 35 wherein said second and third switches are operable to connect said second and third capacitors to said node throughout said integration period.

41. An imager pixel as in claim 35 wherein said second and third switches are operable to connect said second and third capacitors to said node at a time after the beginning of said integration period.

42. An imager pixel as in claim 41 wherein said second and third switches are operable to connect said second and third capacitors to said node at substantially the same time.

43. An imager pixel as in claim 41 wherein said second switch is operable before said third switch to connect said second capacitor to said node before said third capacitor is connected to said node.

44. An imager pixel as in claim 31 wherein said first switch provides said reset voltage to said node through said second switch which is closed during a reset operation.

45. An imager pixel as in claim 32 wherein said reset switch provides said reset voltage to said node through said second and third switches which are closed during a reset operation.

46. An imager pixel cell as in claim 31 wherein said reset switch provides said reset voltage directly to said node.

47. An imager pixel cell as in claim 34 wherein said second switch is operable to selectively connect said second capacitor to said node during at least a portion of a readout period.

48. An imager pixel cell as in claim 35 wherein said third switch is operable to selectively connect said third capacitor to said second capacitor during at least a portion of a readout period.

61. An imager pixel cell as in claim 42 wherein said first capacitor is formed by parasitic capacitance associated by said charge conversion node.

49. An imager pixel cell comprising:

a semiconductor substrate;

a photo-conversion device formed in said substrate, said photo-conversion device having a charge conversion node;

a first capacitor having one terminal connected to said charge conversion node;

a first transistor formed on said substrate for resetting said charge conversion node to a predetermined voltage;

a second transistor formed on said substrate; and

a second capacitor having one terminal connected to said charge conversion node through said second transistor.

50. An imager pixel cell as in claim 49 wherein said first transistor has a source and drain region, one of said source and drain region being said charge conversion node.

51. An imager pixel cell as in claim 49 wherein said photo-conversion device is a photodiode.

52. A imager pixel cell as in claim 49 wherein said second transistor has a source and drain region, one of said source and drain region of said second transistor being said charge conversion node.

53. An imager pixel cell as in claim 49 further comprising:

a third transistor formed on said substrate;

a third capacitor having one terminal connected to said charge conversion node through at least said third transistor.

54. An imager pixel as in claim 53 wherein said one terminal of said third capacitor is connected to said conversion node through said second and third transistors.

55. An imager pixel as in claim 53 wherein said third transistor has source and drain regions, one of which is electrically connected to said one terminal of said third capacitor and the other of which is connected by an electrical conductor to said conversion node.

56. An imager pixel cell as in claim 53 wherein said third transistor has source and drain regions, one of which is electrically connected to one terminal of said third capacitor and the other of which is connected to the source and drain region of said second transistor which is not said charge conversion node.

57. An imager pixel as in claim 56 wherein said first transistor has source and drain regions, one of said source and drain regions of said first transistor being the one of the source and drain regions of said third transistor which is electrically connected to said one terminal of said third capacitor.

58. An imager pixel cell as in claim 49 wherein said second capacitor stores charge generated by said photo-conversion device, when the charge generated by said photo-conversion device reaches a charge level set by a gate voltage of said second transistor.

59. An imager pixel cell as in claim 52 wherein said second capacitor stores charges generated by said photo-conversion device when the charge generated by said photo-conversion device reaches a charge level set by a gate voltage of said second transistor and said third capacitor stores charges generated by said photo conversion device when the charge stored on said second capacitor reaches a charge level set by a gate voltage of said third transistor.

60. An imager pixel as in claim 53 wherein said second capacitor stores charges generated by said photo-conversion device when the charge generated by said photo-conversion device reaches a charge level set by a gate voltage of said second transistor and said third capacitor stores charges generated by said photo-conversion device when the charges generated by said photo-conversion device reach a charge level set by a gate voltage of said third transistor.

62. An imager pixel cell as in claim 49 further comprising a readout transistor having a gate coupled to said charge conversion node, said second transistor causing charges to be redistributed among said first and second capacitors during a readout period.

63. An imager pixel cell as in claim 53 further comprising a readout transistor having a gate coupled to said charge conversion node, said second transistor causing charges to be distributed among said first and second capacitors during a first portion of a readout period, said first and second transistors causing charges to be distributed among said first, second and third capacitors during a second portion of said readout period.

64. A method of operating an imager pixel cell comprising:

generating charges with a photo-conversion device in response to incident light during a charge integration period;

storing said generated charges in a first storage area during said integration period;

storing said generated charges in a second storage area during said integration period when said generated charges exceed a first set limit; and

reading out voltage from said first and second storage areas during a readout period which follows said integration period.

65. A method as in claim 64 further comprising:

storing said generated charges in a third storage area during said integration period when said generated charges exceed a second set limit.

66. A method as in claim 65 wherein said second set limit is higher than said first set limit.

67. A method as in claim 64 wherein said photo-conversion device has a charge accumulation node, said method further comprising resetting said charge accumulation node to a predetermined voltage state during a reset period.

68. A method as in claim 65 wherein said photo-conversion device has a charge accumulation node, said method further comprising resetting said charge accumulation node to a predetermined voltage state during a reset period.

69. A method as in claim 67 further comprising resetting said charge storage areas to predetermined respective voltage states during said reset period.

70. A method as in claim 68 further comprising resetting said charge storage areas to predetermined respective voltage states during said reset period.

71. A method as in claim 64 further comprising setting said first limit with a gate voltage of a transistor which interconnects said first storage area and second storage area.

72. A method as in claim 65 further comprising setting said second limit with a gate voltage of a transistor which interconnects said second and third storage areas.

73. A method as in claim 65 further comprising setting said second limit with a gate voltage of a transistor which interconnects said first and third storage areas.

74. A method as in claim 65 further comprising reading out voltage from said third storage area during said readout period.

75. A method as in claim 71 further comprising controlling gate voltage of said transistor during said readout period to enable the readout of voltage stored in said second storage area.

76. A method as in claim 72 further comprising controlling gate voltage of said transistor during said readout period to enable the readout of voltage stored in said third storage area.

77. A method as in claim 73 further comprising controlling gate voltage of said transistor during said readout period to enable the readout of voltage stored in said third storage area.

78. A method as in claim 67 wherein said resetting is performed by a reset transistor, said method further comprising using said reset transistor to remove charges from at least said first storage area.

79. A method as in claim 67 wherein said resetting is performed by a reset transistor, said method further comprising using said reset transistor to remove charges from at least said first and second storage areas.