Semiconductor wafers having asymmetric edge profiles that facilitate high yield processing by inhibiting particulate contamination and methods of forming same
First Claim
Patent Images
1. A semiconductor wafer having an asymmetric edge profile (EP) extending between an inner edge profile (EPin) and an outer edge profile (EPout) as illustrated by FIG. 1, which is incorporated herein;
- wherein t is a thickness of the semiconductor wafer, φ
1 is an angle in a range between about 30° and
about 85°
, R is a radius of an arc that defines EPin at a point of intersection with a top surface of the semiconductor wafer, and a is an acute angle that represents an angle of intersection between a bottom surface of the semiconductor wafer and a line that is tangent to the arc at a point on EPout; and
wherein;
A1=R(1−
cos φ
1);
A2=R(1−
sin α
)+(t−
Rsin φ
1−
Rcos α
)cotα
;
B1=Rsin φ
1; and
B2=t−
Rsin φ
1.
2 Assignments
0 Petitions
Accused Products
Abstract
Semiconductor wafers utilize asymmetric edge profiles (EP) to facilitate higher yield semiconductor device processing. These edge profiles are configured to reduce the volume of thin film residues that may form on a top surface of a semiconductor wafer at locations adjacent a peripheral edge thereof. These edges profiles are also configured to inhibit redeposition of residue particulates on the top surfaces of the wafers during semiconductor processing steps. Such steps may include surface cleaning and rinsing steps that may include passing a cleaning or rinsing solution across a wafer or batch of wafers that are held by a cartridge and submerged in the solution.
34 Citations
20 Claims
-
1. A semiconductor wafer having an asymmetric edge profile (EP) extending between an inner edge profile (EPin) and an outer edge profile (EPout) as illustrated by FIG. 1, which is incorporated herein;
-
wherein t is a thickness of the semiconductor wafer, φ
1 is an angle in a range between about 30° and
about 85°
, R is a radius of an arc that defines EPin at a point of intersection with a top surface of the semiconductor wafer, and a is an acute angle that represents an angle of intersection between a bottom surface of the semiconductor wafer and a line that is tangent to the arc at a point on EPout; and
wherein;
A1=R(1−
cos φ
1);
A2=R(1−
sin α
)+(t−
Rsin φ
1−
Rcos α
)cotα
;
B1=Rsin φ
1; and
B2=t−
Rsin φ
1. - View Dependent Claims (2, 3, 4, 5)
-
-
6. A semiconductor wafer having an asymmetric edge profile (EP) extending between an inner edge profile (EPin) and an outer edge profile (EPout) as illustrated by FIG. 1, which is incorporated herein;
- wherein φ
1 is an angle in a range between about 30° and
about 85°
; and
wherein R is in a range between about 0.23t and about 0.5t. - View Dependent Claims (7, 8, 9)
- wherein φ
-
10. A semiconductor wafer having an asymmetric edge profile (EP) extending between an inner edge profile (EPin) and an outer edge profile (EPout) as illustrated by FIG. 1, which is incorporated herein.
-
11. A semiconductor wafer having an asymmetric edge profile that consists of an arc, which has a radius R that sweeps a downward angle of 2φ
- from a top surface of the wafer, and a straight line that is orthogonal to R and extends from one end of the arc to a bottom surface of the wafer.
- View Dependent Claims (12, 13, 14)
-
15. A method of forming a semiconductor wafer, comprising the steps of:
-
slicing a semiconductor ingot into at least one semiconductor wafer having a top surface and a bottom surface; and
grinding a peripheral edge of the at least one semiconductor wafer to define an asymmetric edge profile (EP) extending between an inner edge profile (EPin) and an outer edge profile (EPout) as illustrated by FIG. 1, which is incorporated herein. - View Dependent Claims (16, 17)
-
-
18. A semiconductor wafer having an asymmetric edge profile (EP2) extending between an inner edge profile (EP2in) and an outer edge profile (EP2out) as illustrated by FIG. 2, which is incorporated herein;
- wherein φ
1 and φ
2 are angles in a range between about 30° and
about 85°
;
wherein φ
1<
φ
2; and
wherein R is in a range between about 0.23t and about 0.5t.
- wherein φ
-
19. A semiconductor wafer having an asymmetric edge profile (EP2) extending between an inner edge profile (EP2in) and an outer edge profile (EP2out) as illustrated by FIG. 2, which is incorporated herein;
-
wherein t is a thickness of the semiconductor wafer, φ
1 is an angle in a range between about 30° and
about 85°
, φ
2 is greater than φ
1 and less than about 85°
, R is a radius of an arc that defines EP2in at a point of intersection with a top surface of the semiconductor wafer, and α
is an acute angle that represents an angle of intersection between a bottom surface of the semiconductor wafer and a line that is tangent to the arc at a point on EP2out; and
wherein;
A1=R(1−
cos φ
1);
A2=R(1−
sin α
)+(B2−
Rcos α
)cotα
;
B1=Rsin φ
1; and
B2=t−
Rsin φ
1.
-
-
20. A method of forming a semiconductor wafer, comprising the steps of:
-
slicing a semiconductor ingot into at least one semiconductor wafer having a top surface and a bottom surface; and
grinding a peripheral edge of the at least one semiconductor wafer to define an asymmetric edge profile (EP2) extending between an inner edge profile (EP2in) and an outer edge profile (EP2out) as illustrated by FIG. 2, which is incorporated herein;
wherein φ
1 is an angle in a range between about 30° and
about 85°
; and
wherein φ
φ
2 is an angle that is greater than φ
1 and less than about 85°
.
-
Specification
-
- Resources
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Current AssigneeSamsung Electronics Co. Ltd.
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Original AssigneeSamsung Electronics Co. Ltd.
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InventorsKim, Gi-Jung, Chon, Sang-Mun, Heo, Tae-Yeol, Kim, Woo-Serk
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Granted Patent
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Time in Patent OfficeDays
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Field of Search
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US Class Current257/1
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CPC Class CodesH01L 21/02021 Edge treatment, chamferingY10T 428/12674 Ge- or Si-base component
