Semiconductor device

• US 20040041256A1
• Filed: 08/26/2003
• Published: 03/04/2004
• Est. Priority Date: 08/28/2002
• Status: Active Grant

• Current Assignee: Collabo Innovations, Inc. (Wi-LAN Inc.)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Yoshikawa, Noriyuki, Takehara, Hideki, Kanazawa, Kunihiko
• Granted Patent: US 6,794,747 B2
• Time in Patent Office: Days
• US Class Current: 257/712
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/16152 Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H01L 2924/3025 Electromagnetic shielding
• CPC Class Codes: H05K 1/0206 : by printed thermal vias
• CPC Class Codes: H05K 1/0306 : Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 1/183 : Components mounted in and supported by recessed areas of the printed circuit board
• CPC Class Codes: H05K 2203/049 : Wire bonding
• CPC Class Codes: H05K 3/4061 : for via connections in inorganic insulating substrates
• CPC Class Codes: H05K 3/4605 : made from inorganic insulating material

Abstract

The present invention provides a semiconductor device comprising as a core substrate a high thermo conductive ceramic substrate having circuit patterns on opposed surfaces. The high thermo conductive ceramic substrate has on one surface a first circuit board of at least one layer having a first cavity structure, and on the other surface a second circuit board of at least one layer having a second cavity structure. A first active element is mounted on the circuit pattern on the high thermo conductive ceramic substrate within the first cavity, a second active element is mounted on the circuit pattern on the high thermo conductive ceramic substrate within the second cavity, an external electrode is integrated with the surface of the second circuit board, and the first circuit board surface is equipped with a cap or sealed with resin. A heat dissipation via is formed on the second circuit board, the high thermo conductive ceramic substrate and the external electrode on the surface of the second circuit board are connected thermally to each other, and heat of at least one active element selected from the first active element and the second active element is dissipated outward through the high thermo conductive ceramic substrate, the heat dissipation via and the external electrode on the surface of the second circuit board. The semiconductor device is downsized while securing transverse strength and heat dissipation characteristics of a heat-generating semiconductor element.

Claims

1. A semiconductor device comprising:

as a core substrate of a high thermo conductive ceramic substrate having circuit patterns on opposed surfaces,

the high thermo conductive ceramic substrate having on one surface a first circuit board of at least one layer having a first cavity structure, and on the other surface a second circuit board of at least one layer having a second cavity structure;

a first active element mounted on the circuit pattern on the high thermo conductive ceramic substrate within the first cavity;

a second active element mounted on the circuit pattern on the high thermo conductive ceramic substrate within the second cavity; and

an external electrode integrated with the surface of the second circuit board,

the first circuit board surface being covered;

wherein

a heat dissipation via is formed on the second circuit board, the high thermo conductive ceramic substrate and the external electrode on the surface of the second circuit board are connected thermally to each other, and heat of at least one active element selected from the first active element and the second active element is dissipated outward through the high thermo conductive ceramic substrate, the heat dissipation via and the external electrode on the surface of the second circuit board.

2. The semiconductor device according to claim 1, wherein on a lower surface of the second circuit board, a second high thermo conductive ceramic substrate made of the same material as the first high thermo conductive ceramic substrate and having a third cavity structure is formed so that the second cavity and the third cavity are overlapped.

3. The semiconductor device according to claim 1, wherein either the first active element or the second semiconductor element is a high-frequency power semiconductor element, and the other active element is a controlling semiconductor element having a function of driving and controlling the power semiconductor element.

4. The semiconductor device according to claim 1, wherein at least one passive element selected from the group consisting of an inductor, a capacitor and a resistor is packaged on the surface of the first circuit board.

5. The semiconductor device according to claim 1, wherein either the first active element or the second active element is a filter element, and the other active element is a switching element.

6. The semiconductor device according to claim 1, wherein the first circuit board has on its surface a region for mounting a power semiconductor element, and a via hole filled with a metal or a metal-containing resin is formed in the region so as to be connected thermally with the high thermo conductive ceramic substrate.

7. The semiconductor device according to claim 1, wherein the first circuit board and the second circuit board are at least one kind of circuit board selected from the group consisting of a ceramic substrate and a substrate prepared by impregnating a resin in a reinforcing fiber structure.

8. The semiconductor device according to claim 1, wherein a plurality of the cavity structures are provided on the both surfaces of the high thermo conductive ceramic substrate.

9. The semiconductor device according to claim 8, wherein an electroconductive via or a circuit pattern to be connected to a ground is formed on an inner layer or a surface layer of spacing between the plural cavities of the first circuit board.

10. The semiconductor device according to claim 8, wherein an electroconductive via or a circuit pattern to be connected to a ground is formed on an inner layer or a surface layer of spacing between the plural cavities of the second circuit board.

11. The semiconductor device according to claim 8, wherein a power semiconductor element and a filter element are mounted respectively on the circuit pattern on the high thermo conductive ceramic substrate within the cavity of the first circuit board.

12. The semiconductor device according to claim 11, wherein the filter element mounted on the first circuit board is packaged by flip-chip bonding.

13. The semiconductor device according to claim 8, wherein a controlling element and a switching element are mounted on the circuit pattern on the high thermo conductive ceramic substrate within cavities of the second circuit board.

14. The semiconductor device according to claim 13, wherein the controlling element or the switching element is packaged by flip-chip bonding.

15. The semiconductor device according to claim 1, wherein the heat dissipation external electrode on the surface of the second circuit board is connected to a ground.

16. The semiconductor device according to claim 1, wherein the high thermo conductive ceramic substrate comprises a first ceramic substrate and a second ceramic substrate, and a plurality of stepped cavities are formed in the second ceramic substrate.

17. The semiconductor device according to claim 16, wherein circuit patterns to be connected to a ground are formed in regions in the vicinity of the cavities of the first and second ceramic substrates, at the steps of the cavities and regions in the vicinity of the cavity steps, a region in the back face of the cavity for a filter element of the high thermo conductive ceramic substrate, and among the plural cavities on the second ceramic substrate;

the controlling semiconductor element and the switching element are mounted by flip-chip bonding onto the circuit pattern of the high thermo conductive ceramic substrate within a cavity of the first ceramic substrate, a power semiconductor element and at least one filter element selected from the group consisting of a SAW filter element, a dielectric filter element and a LC filter element, are mounted on the circuit pattern on the high thermo conductive ceramic substrate within the cavity of the second ceramic substrate, the SAW filter element is mounted by flip-chip bonding; and

the circuit pattern at the cavity steps of the second ceramic substrate and a metal plate are adhered by an electroconductive adhesive and sealed.

18. The semiconductor device according to claim 1, wherein the high thermo conductive ceramic substrate is made of a material selected from the group consisting of alumina, aluminum nitride, graphite, silicon carbide, and boron nitride.

19. The semiconductor device according to claim 1, wherein the heat dissipation via is formed by being filled with an electroconductive paste containing a metal filler of 65 wt % to 95 wt % and a thermosetting resin of 5 wt % to 35 wt % and curing the electroconductive paste.

20. The semiconductor device according to claim 1, wherein the heat dissipation via is arranged on the back face sides or in the vicinity of the first active element and the second active element.