Display processor integrated circuit with on-chip programmable logic for implementing custom enhancement functions

• US 20040041918A1
• Filed: 09/04/2002
• Published: 03/04/2004
• Est. Priority Date: 09/04/2002
• Status: Active Grant

• Current Assignee: F Poszat Hu LLC (Intellectual Ventures LLC), VLMA Microsystems Corporation
• Original Assignee: Denace Enterprise Co LLC (Intellectual Ventures LLC)
• Inventors: Chan, Andrew K., Chan, Thomas M., Raftopoulos, Harry J.
• Granted Patent: US 7,782,398 B2
• Time in Patent Office: Days
• US Class Current: 348/222.1
• CPC Class Codes: G09G 2310/0229 De-interlacing
• CPC Class Codes: G09G 2320/106 Determination of movement vectors or equivalent parameters within the image
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: H04N 5/21 Circuitry for suppressing or minimising disturbance, e.g. moiré or halo

Abstract

A display processor integrated circuit (for example, for a television or for a digital camera) includes a display processor portion and an on-chip programmable logic portion. The on-chip programmable logic portion can be configured or programmed to implement custom video and/or image enhancement functions. Accordingly, an individual television or camera manufacturer can have his/her own custom enhancement function incorporated into the display processor integrated circuit by having the programmable logic portion configured or programmed appropriately. In one embodiment, the programming of the programmable logic portion involves changing just one mask, thereby reducing the cost, complexity and time associated with implementing tyhe custom video/image enhancement function.

Claims

1. A display processor integrated circuit, comprising:

a display processor portion; and

a programmable logic portion coupled to the display processor portion, the programmable logic portion being programmed to implement a video enhancement algorithm.

2. The display processor integrated circuit of claim 1, wherein the video enhancement algorithm is taken from the group consisting of:

a peaking algorithm, a luminous processing algorithm, a chroma processing alogorithm, a brightness enhancing algorithm, a sharpness enhancing algorithm, an upscaling algorithm, a downscaling algorithm, a noise reduction algorithm, a 2;

2 pulldown algorithm, a 3;

2 pulldown algorithm, a VBI information extracting algorithm.

3. The display processor integrated circuit of claim 1, wherein the display processor integrated circuit receives a televion video signal from an analog-to-digital converter, and wherein the display processor integrated circuit outputs a processed television video signal to a driver, the driver being one of a CRT driver, an LCD driver and a plasma display driver.

4. The display processor integrated circuit of claim 1, wherein the display processor integrated circuit is part of a HDTV television.

5. The display processor integrated circuit of claim 1, wherein the display processor integrated circuit is part of a digitally-enhanced television, and wherein the digitally-enhanced television receives one of an NTSC and a PAL signal.

6. The display processor integrated circuit of claim 1, wherein the programmable logic portion comprises one of an SRAM-based programmable logic core, an antifuse-based programmable logic core, an EEPROM-based programmable logic core, a Flash-based programmable logic core, and a mask-programmable logic core.

7. The display processor integrated circuit of claim 1, wherein the programmable logic portion includes a dual-port SRAM memory.

8. The display processor integrated circuit of claim 1, wherein the programmable logic portion includes a configurable SRAM memory block, the configurable SRAM memory block having a configurable width.

9. The display processor integrated circuit of claim 1, wherein the display processor portion includes a memory controller for interfacing with an external memory, the programmable logic portion being coupled to the memory controller.

10. The display processor integrated circuit of claim 1, wherein the programmable logic portion contains an amount of logic functionally equivalent to approximately at least 50,000 gates.

11. The display processor integrated circuit of claim 1, wherein the programmable logic portion is programmed by customizing only one mask of a multi-mask process, the multi-mask process being used to fabricate the display processor integrated circuit.

12. A method, comprising:

manufacturing a first and a second display processor integrated circuit, each of the first and second display processor integrated circuits having display processor portions that are substantially identical to one another, each of the first and second display processor integrated circuits comprising programmable logic portions;

selling the first display processor integrated circuit to a first customer, the first display processor integrated circuit being programmed in a first way; and

selling the second display processor integrated circuit to a second customer, the second display processor integrated circuit being programmed in a second way.

13. The method of claim 12, wherein the programming of the first display processor integrated circuit in the first way results in the first display processor integrated circuit being able to perform a first video enhancement function, and wherein the programming of the second display processor integrated circuit in the second way results in the second display processor integrated circuit being able to perform a second video enhancement function, the first display processor integrated circuit not being able to perform the second video enhancement function, the second display processor integrated circuit not being able to perform the first video enhancement function.

14. The method of claim 12, wherein the programmable logic portion contains an amount of logic functionally equivalent to approximately at least 50,000 gates.

15. The method of claim 12, wherein the programming of the first display processor integrated circuit in the first way involves changing a mask used during the manufacturing of the first display processor integrate circuit, and wherein the programming of the second display processor integrated circuit in the second way involves changing a mask used during the manufacturing of the second display processor integrate circuit.

16. A integrated circuit disposed in a digital camera or camcorder, the integrated circuit comprising:

a display processor portion; and

a programmable logic portion coupled to the display processor portion, the programmable logic portion being programmed to implement an image enhancement algorithm.

17. The integrated circuit of claim 16, wherein the image enhancement algorithm is taken from the group consisting of:

a skin tone detection algorithm, a color correction algorithm, a gamma correction algorithm, an edge enhancement algorithm, and an NTSC/PAL encoder.