ONE-DEVICE NON-VOLATILE RANDOM ACCESS MEMORY CELL

• US 20040042268A1
• Filed: 08/30/2002
• Published: 03/04/2004
• Est. Priority Date: 08/30/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bhattacharyya, Arup
• Granted Patent: US 6,903,969 B2
• Time in Patent Office: Days
• US Class Current: 365/185.08
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7886 Hot carrier produced by avalanche breakdown of a PN junction, e.g. FAMOS
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

One aspect of the present subject matter relates to a one-device non-volatile memory cell. The memory cell includes a body region, a first diffusion region and a second diffusion region formed in the body region. A channel region is formed in the body region between the first diffusion region and the second diffusion region. The memory cell includes a gate insulator stack formed above the channel region, and a gate to connect to a word line. The gate insulator stack includes a floating plate to selectively hold a charge. The floating plate is connected to the second diffusion region. The memory cell includes a diode that connects the body region to the second diffusion region such that the floating plate is charged when the diode is reversed biased. Other aspects are provided herein.

Claims

1. A one-device non-volatile memory cell, comprising:

a body region;

a first diffusion region formed in the body region;

a second diffusion region formed in the body region such that a channel region is formed in the body region between the first diffusion region and the second diffusion region;

a gate insulator stack formed above the channel region, the gate insulator stack including a floating plate to selectively hold a charge, the floating plate being connected to the second diffusion region;

a gate formed above the gate insulator stack such that the gate insulator stack is disposed between the gate and the channel region; and

a diode connecting the body region to the second diffusion region.

2. The memory cell of claim 1, wherein:

a p type semiconductor material forms the body region;

an n+ semiconductor material forms the first diffusion region and the second diffusion region; and

the diode includes a lateral p-n+ diode between the body region and the second diffusion region.

3. The memory cell of claim 1, wherein:

an n type semiconductor material forms the body region;

an p+ semiconductor material forms the first diffusion region and the second diffusion region; and

the diode includes a lateral p+-n diode between the second diffusion region and the body region.

4. The memory cell of claim 1, wherein the floating plate includes a layer of metal silicide.

5. The memory cell of claim 4, wherein the floating plate further includes a layer of metal oxide to provide shallow traps to hold charge in the gate insulator stack.

6. The memory cell of claim 4, wherein the layer of metal silicide electrically contacts the second diffusion region such that the second diffusion region is electrically connected to the floating plate.

7. The memory cell of claim 1, further comprising a Schottky diode connecting the body region to the floating plate such that the floating plate is discharged through the Schottky diode when the Schottky diode is forward biased.

8. The memory cell of claim 7, wherein the Schottky diode is formed by a layer of metal silicide that electrically contacts the body region.

9. The memory cell of claim 1, wherein the body region includes a substrate.

10. The memory cell of claim 1, wherein the body region includes a well region.

11. A one-device non-volatile memory cell, comprising:

a body region;

a first diffusion region formed in the body region;

a second diffusion region formed in the body region such that a channel region is formed in the body region between the first diffusion region and the second diffusion region;

a gate insulator stack formed above the channel region, the gate insulator stack including a floating plate to selectively hold a charge, the floating plate being ohmically connected to the second diffusion region;

a gate formed above the gate insulator stack such that the gate insulator stack is disposed between the gate and the channel region;

a built-in lateral diode connecting the body region to the second diffusion region; and

a built-in Schottky diode connecting the body region to the floating plate.

12. The memory cell of claim 11, wherein:

the floating plate includes a layer of metal silicide that contacts the second diffusion region and the body region; and

the built-in Schottky diode is formed by the contact of the metal silicide region with the body region.

13. The memory cell of claim 11, wherein the first diffusion region and the second diffusion region are formed by an asymmetric doping mask that provides a contact between the body region and a metal suicide to form a Schottky diode and that provides a semiconductor junction diode between the body region and the second diffusion region.

14. A one-device non-volatile memory cell, comprising:

a body region;

a first diffusion region formed in the body region to connect to a bit line;

a second diffusion region formed in the body region such that a channel region is formed in the body region between the first diffusion region and the second diffusion region;

a first tunnel oxide region formed above the channel region to provide a lower charge blocking layer;

a floating plate formed above the first oxide region and ohmically connected to the second diffusion region;

a second tunnel oxide region formed above the floating plate to provide an upper charge blocking layer;

a gate to connect to a word line, the gate being formed above the second tunnel oxide region; and

a diode connecting the body region to the second diffusion region.

15. The cell of claim 14, wherein the floating plate includes a layer of metal silicide.

16. The cell of claim 15, wherein the layer of metal silicide includes a layer of transition metal silicide.

17. The cell of claim 14, further comprising a layer of metal oxide formed between the first oxide region and the second oxide region to function as shallow traps for holding charge in the floating plate over the channel region.

18. The cell of claim 17, wherein the layer of metal oxide includes a layer of transition metal oxide.

19. The cell of claim 14, wherein the diode includes a lateral semiconductor junction diode between the body region and the second diffusion region such that the floating plate is charged when the diode is reversed biased.

20. The cell of claim 14, further comprising a Schottky diode between the second diffusion region and the body region such that the floating plate is discharged when the Schottky diode is forward biased.

21. A one-device non-volatile memory cell, comprising:

a substrate including a body region, a first diffusion region, and a second diffusion region, wherein the first diffusion region and the second diffusion region provide a channel region in the body region;

a gate insulator stack formed over the channel, including;

a first tunnel oxide region formed above the channel region to provide a lower charge blocking layer;

a floating plate formed by a combination of a metal silicide layer and a metal oxide layer formed on the first tunnel oxide region, wherein the metal silicide layer is ohmically connected to the second diffusion region;

a second tunnel oxide region formed above the combination of the metal silicide layer and the metal oxide layer to provide an upper charge blocking layer;

a gate formed above the second tunnel oxide region; and

a diode connecting the body region to the second diffusion region.

22. The memory cell of claim 21, wherein the combination of a metal silicide layer and a metal oxide layer includes a combination of a transition metal silicide layer and a transition metal oxide layer.

23. The memory cell of claim 21, wherein the diode includes a lateral junction diode connecting the body region to the second diffusion region such that the floating plate is charged when the lateral junction diode is reversed biased.

24. The memory cell of claim 23, further comprising a Schottky diode formed by a junction between the metal silicide layer and the body region, wherein providing a forward bias to the Schottky diode discharges the floating plate.

25. A one-device non-volatile memory cell, comprising:

a substrate including a body region, a first diffusion region, and a second diffusion region, wherein the first diffusion region and the second diffusion region provide a channel region in the body region;

a gate insulator stack formed over the channel, including;

a first tunnel oxide region formed above the channel region to provide a lower charge blocking layer;

a floating plate formed by a combination of a metal silicide layer and a metal oxide layer formed on the first tunnel oxide region, wherein the metal silicide layer contacts the second diffusion region;

a second tunnel oxide region formed above the combination of the metal silicide layer and the metal oxide layer to provide an upper charge blocking layer;

a gate formed above the second tunnel oxide region;

a lateral semiconductor junction diode connecting the body region to the second diffusion region such that the floating plate is charged when the junction diode is reversed biased; and

a Schottky diode formed by the contact between the metal silicide layer and the body region such that the floating plate is discharged when the Schottky diode is forward biased.

26. The memory cell of claim 25, wherein the combination of a metal silicide layer and a metal oxide layer includes a combination of a transition metal silicide layer and a transition metal oxide layer.

27. The memory cell of claim 25, wherein an asymmetric doping mask is used to form the junction diode and to provide means for the metal silicide layer to contact both the body region and the second diffusion region.

28. A one-device non-volatile memory cell, comprising:

a substrate including a body region, a first diffusion region, and a second diffusion region, wherein the first diffusion region and the second diffusion region provide a channel region in the body region;

a gate;

a gate insulator stack between the substrate and the gate, and formed over the channel, including;

charge storage means for holding a charge to change a threshold voltage of the cell; and

charge blocking means for preventing significant charge leakage from the charge storage means to the gate and from the charge storage means to the substrate;

means for providing an ohmic connection between the charge storage means and the second diffusion layer; and

means for charging and discharging the charge storage means through the ohmic connection.

29. The memory cell of claim 28, wherein the charge storage means includes a metal oxide layer.

30. The memory cell of claim 28, wherein the means for providing an ohmic connection between the charge storage means and the second diffusion layer includes a metal suicide layer within the gate insulator stack that contacts the second diffusion region.

31. The memory cell of claim 28, wherein the means for charging and discharging the charge storage means through the ohmic connection includes:

a lateral semiconductor junction diode between the body region and the second diffusion region that charges the charge storage means when reversed biased; and

a Schottky diode between the body region and the charge storage means that discharges the charge storage means when forward biased.

32. A memory array, comprising:

a number of memory cell transistors;

each of the memory cell transistors including a body region, a first diffusion region, a second diffusion region, a gate, a floating plate and at least one diode;

the floating plate being disposed between the body region and the gate to store a charge that changes a threshold voltage of the memory cell transistor;

the second diffusion region being ohmically connected to the floating plate; and

the at least one diode being connected to the source region and to the body region such that a reverse bias charges the floating plate and a forward bias discharges the floating plate.

33. The memory cell of claim 32, wherein the memory cell transistors are arranged into a number of rows and a number of columns,

the first diffusion region of each of the memory cell transistors in a first column is connected to a first bit line;

and

the gate of each of the memory cell transistors in a first row is connected to a first word line.

34. The memory array of claim 32, wherein the at least one diode includes a built-in semiconductor junction diode between the body region and the source region such that the junction diode charges the floating plate when reversed biased.

35. The memory array of claim 32, wherein the at least one diode includes a Schottky diode connected to the floating plate and the body region such that a forward biased Schottky diode discharges the floating plate.

36. The memory array of claim 32, wherein the floating plate includes a layer of metal silicide that contacts the source region.

37. The memory array of claim 36, wherein the layer of metal suicide includes a layer of transition metal silicide.

38. The memory array of claim 36, further comprising a layer of metal oxide to form charge centers that enhance charge storage in the floating plate of each of the memory cell transistors.

39. The memory array of claim 38, wherein the layer of metal oxide includes a layer of transition metal oxide.

40. A memory array, comprising:

a number of memory cell transistors;

each of the memory cell transistors including a body region, a first diffusion region, a second diffusion region, a gate insulator stack formed above the channel region, and a gate formed above the gate insulator stack;

the gate insulator stack including a floating plate to selectively hold a charge;

the floating plate being ohmically connected to the second diffusion region;

a built-in lateral diode connecting the body region to the second diffusion region such that the floating plate is charged when the diode is reversed biased; and

a built-in Schottky diode connecting the body region to the floating plate such that the floating plate is discharged when the built-in Schottky diode is forward biased.

41. The memory array of claim 40, wherein:

the floating plate includes a layer of metal silicide that contacts the second diffusion region and the body region; and

the built-in Schottky diode is formed by the contact of the metal silicide region with the body region.

42. The memory array of claim 40, wherein the first diffusion region and the second diffusion region are formed by an asymmetric doping mask that provides a contact between the body region and a metal silicide to form a Schottky diode and that provides a semiconductor junction diode between the body region and the second diffusion region.

43. A memory device, comprising:

a memory array including a number of memory cell transistors arranged into a number of rows and a number of columns, wherein;

each of the memory cell transistors includes a body region, a first diffusion region, a second diffusion region, a gate, a floating plate and at least one diode;

the floating plate is disposed between the body region and the gate to store a charge that changes a threshold voltage of the memory cell transistor;

the second diffusion region is ohmically connected to the floating plate and functions as a storage node;

the at least one diode is connected to the source region and to the body region such that a reverse bias charges the floating plate and a forward bias discharges the floating plate;

the first diffusion region of each of the memory cell transistors in a first column is connected to a first bit line; and

the gate of each of the memory cell transistors in a first row is connected to a first word line; and

read/write control circuitry operably connected to the memory array, including;

word line circuitry to provide a logic potential on a selected word line in the memory array;

bit line circuitry to provide a logic potential on a selected bit line in the memory array;

body circuitry to provide a logic potential on a body region of the memory array; and

sensing circuitry for reading the storage node of the memory cell.

44. The memory device of claim 43, wherein the floating plate includes a layer of metal silicide that contacts the second diffusion region.

45. The memory device of claim 44, wherein the floating plate further includes a layer of metal oxide in contact with the metal silicide to provide shallow traps to hold charge.

46. The memory device of claim 43, wherein the memory device forms part of an electronic system that includes a processor to communicate with the memory device.

47. An electronic system, comprising:

a processor; and

a memory device to communicate with the processor, wherein the memory device includes an array of memory cells, wherein each memory cell comprises;

a body region;

a first diffusion region formed in the body region;

a second diffusion region formed in the body region such that a channel region is formed in the body region between the first diffusion region and the second diffusion region;

a gate insulator stack formed above the channel region, the gate insulator stack including a floating plate to selectively hold a charge, the floating plate being electrically connected to the second diffusion region;

a gate formed above the gate insulator stack such that the gate insulator stack is disposed between the gate and the channel region; and

a diode connecting the body region to the second diffusion region such that the floating plate in the gate insulator stack is charged when the diode is reversed biased.

48. The system of claim 47, wherein the floating plate includes a layer of metal silicide.

49. The system of claim 48, wherein the floating plate further includes a layer of metal oxide to provide shallow traps to hold charge in the gate insulator stack.

50. The system of claim 48, wherein the layer of metal silicide electrically contacts the second diffusion region such that the second diffusion region is electrically connected to the floating plate.

51. The system of claim 47, further comprising a Schottky diode connecting the body region to the floating plate such that the floating plate is discharged through the Schottky diode when the Schottky diode is forward biased.

52. The system of claim 51, wherein the Schottky diode is formed by a layer of metal silicide that electrically contacts the body region.

53. A method of operating a one device non-volatile memory cell that includes a transistor having a body region, a first diffusion region in the body region to connect with a bit line, a second diffusion region in the body region functioning as a storage node, a gate to connect with a word line, a floating plate disposed within a gate insulator stack between the gate and the body region and ohmically connected to the second diffusion region, and at least one diode connecting the second diffusion region and the body region, the method comprising:

writing a logic high value to the cell by providing a logic high bit line potential, a logic high word line potential, and a logic low substrate potential to reverse bias the at least one diode to charge the floating plate;

writing a logic low value to the cell by providing a logic low bit line potential, a logic low word line potential, and a logic high substrate potential to forward bias the at least one diode to discharge the floating plate; and

reading a logic value of the storage node by providing a logic high word line potential and a logic low substrate potential, and by sensing a resulting bit line potential to determine if the logic high word line potential turned on the transistor.

54. The method of claim 53, wherein the at least one diode includes a lateral semiconductor junction diode that charges the floating plate to write the logic high value to the cell when a reverse bias potential is applied.

55. The method of claim 54, wherein the junction diode includes a p-n+ diode that provides electrons to the floating plate when the p-n+ diode is reversed biased.

56. The method of claim 53, wherein the at least one diode includes a Schottky diode that discharges the floating plate when a forward bias potential is applied.

57. The method of claim 53, wherein the Schottky diode provides holes under a low field to quickly neutralize electrons stored on the floating plate.

58. A method of fabricating a one device non-volatile memory cell, comprising:

providing a substrate;

depositing a first tunnel oxide layer on the substrate;

removing a portion of the first tunnel oxide layer over a desired second diffusion region;

depositing a metal silicide layer on the gate oxide layer such that the metal silicide layer contacts the body layer at the desired second diffusion region and does not extend over a desired first diffusion region;

depositing a metal oxide layer on the metal silicide layer;

depositing a second tunnel oxide layer on the metal oxide layer;

depositing a polysilicon layer on the second gate oxide layer;

defining a gate by selectively removing portions of the polysilicon layer; and

implanting ions to define the desired first diffusion region, the desired second diffusion region, and a body region.

59. The method of claim 58, wherein depositing a metal silicide layer includes depositing a transition-metal silicide layer.

60. The method of claim 58, wherein depositing a metal oxide layer includes depositing a transition-metal oxide layer.

61. The method of claim 58, wherein depositing a metal silicide layer includes contacting the substrate to form a Schottky diode between the substrate and the metal silicide layer.

62. The method of claim 58, wherein implanting ions includes using an asymmetric diffusion mask to form a lateral junction diode between the substrate and the second diffusion region and to form a Schottky diode between the substrate and the metal silicide layer.