×

Novolatile semiconductor memory having multilayer gate structure

  • US 20040042272A1
  • Filed: 09/30/2002
  • Published: 03/04/2004
  • Est. Priority Date: 08/30/2002
  • Status: Abandoned Application
First Claim
Patent Images

1. A semiconductor memory device comprising:

  • memory cells arranged in matrix, adjacent memory cells in a column direction having one of a source and a drain in common;

    source lines to each of which sources of memory cells of adjacent two columns are connected;

    drain lines to each of which drains of memory cells of adjacent two columns are connected, drains of memory cells of two columns connected to the source line being connected to different drain lines, respectively; and

    a control gate line to which gates of adjacent memory cells in a row direction are connected.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×