Novolatile semiconductor memory having multilayer gate structure
First Claim
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1. A semiconductor memory device comprising:
- memory cells arranged in matrix, adjacent memory cells in a column direction having one of a source and a drain in common;
source lines to each of which sources of memory cells of adjacent two columns are connected;
drain lines to each of which drains of memory cells of adjacent two columns are connected, drains of memory cells of two columns connected to the source line being connected to different drain lines, respectively; and
a control gate line to which gates of adjacent memory cells in a row direction are connected.
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Abstract
A semiconductor memory device includes memory cells, source lines, drain lines, and control gate lines. The memory cells are arranged in matrix. Adjacent memory cells in the column direction have one of a source and a drain in common. The sources of memory cells of adjacent two columns are connected to a common source line. The drains of memory cells of adjacent two columns are connected to a common drain line. The drains of memory cells of two columns connected to the source line are connected to different drain lines, respectively. The gates of adjacent memory cells in the row direction are connected to a common control gate line.
63 Citations
19 Claims
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1. A semiconductor memory device comprising:
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memory cells arranged in matrix, adjacent memory cells in a column direction having one of a source and a drain in common;
source lines to each of which sources of memory cells of adjacent two columns are connected;
drain lines to each of which drains of memory cells of adjacent two columns are connected, drains of memory cells of two columns connected to the source line being connected to different drain lines, respectively; and
a control gate line to which gates of adjacent memory cells in a row direction are connected. - View Dependent Claims (2, 3, 4, 12)
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5. A semiconductor memory device comprising:
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memory cells arranged in matrix, adjacent memory cells in a column direction having one of one end and other end of a current path in common;
bit lines to each of which one end of each of current paths of memory cells in adjacent two columns or other end thereof is connected, the other ends of the current paths of the memory cells being connected to different bit lines when the one end of each of the current paths of the memory cells is connected to a common one of the bit lines; and
control gate lines to each of which gates of adjacent memory cells in a row direction are connected. - View Dependent Claims (6, 7, 8, 13)
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9. A semiconductor memory device comprising:
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a memory cell array including a plurality of first memory cell units arranged in matrix, each of the first memory cell units having four memory cells arrange in matrix, the four memory cells having current paths whose ends are connected to one another;
second memory cell units each including four memory cells, the four memory cells corresponding to closest four memory cells of adjacent four first memory cell units, other ends of current paths of the closest four memory cells being connected to one another;
a first wire which connects ends of current paths of first memory cell units in same column;
a second wire which connects other ends of current paths of second memory cell units in same column; and
a control gate line which connects gates of memory cells in same row. - View Dependent Claims (10, 11, 14)
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15. A semiconductor memory device comprising:
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element isolation regions arranged in a staggered format in a semiconductor substrate, a longitudinal direction of the element isolation regions being equal to a first direction;
a plurality of control gate lines formed on the semiconductor substrate along a second direction perpendicular to the first direction, two control gate lines passing across each of the element isolation regions, and an n-th (n is natural number larger than one) control gate line alternately passing across same element isolation regions as those across which (n+1)-th and (n−
1)-th control gate lines pass; and
a contact region formed between adjacent element isolation regions in the first direction. - View Dependent Claims (16, 17, 18, 19)
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Specification