Semiconductor device

• US 20040042292A1
• Filed: 02/27/2003
• Published: 03/04/2004
• Est. Priority Date: 08/27/2002
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Sakata, Takeshi, Matsuoka, Hideyuki
• Granted Patent: US 6,862,235 B2
• Time in Patent Office: Days
• US Class Current: 365/202
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers

Abstract

There is disclosed a write operation of a MRAM in which a current necessary for inverting magnetization of an MTJ element has to be passed through a data line and therefore current consumption is large. The write operation comprises: comparing input data DI with read data GO read from a memory cell array and encoding the input data DI to form write data GI by a data encoder WC; and decoding the read data GO by a data decoder RD to form output data DO. In a nonvolatile semiconductor memory in which the current is passed through the data line to write data into a memory cell, the number of bits to be written during the write operation is reduced, and the current consumption can be reduced. This can realize the MRAM including a low-power highly-integrated memory.

Claims

1. A semiconductor device comprising:

a memory array including a plurality of memory cells;

a data encoder which compares read data of a plurality of memory cells selected from the plurality of memory cells with input data, and encodes the input data to form write data; and

a data decoder which decodes the read data.

2. The semiconductor device according to claim 1, wherein the data encoder encodes the input data so that the number of memory cells in which the data is inverted is reduced by half or more in the plurality of selected memory cells.

3. The semiconductor device according to claim 2, wherein the data encoder comprises:

a judgment circuit for judging whether or not the number of bits in which the read data agrees with the input data is larger than the half of the number of bits of the input data.

4. The semiconductor device according to claim 1, comprising:

a plurality of data encoders.

5. The semiconductor device according to claim 4, comprising a plurality of memory arrays,

wherein the plurality of data encoders are disposed in the plurality of memory arrays.

6. The semiconductor device according to claim 1, wherein the write data has the number of bits larger than that of the input data.

7. The semiconductor device according to claim 6, wherein the data decoder controls another bit in accordance with a specific bit in the read data.

8. The semiconductor device according to claim 1, wherein only the memory cell in which the data is inverted is subjected to a write operation in the plurality of selected memory cells.

9. The semiconductor device according to claim 1, wherein the memory array comprises a plurality of data lines which intersect with a plurality of word lines,

the plurality of memory cells are disposed in desired intersections of the plurality of word lines with the plurality of data lines, and

information of a non-selected memory cell connected to the same word line as that connected to the plurality of selected memory cells is not destroyed during the reading of the data from the plurality of selected memory cells in the plurality of memory cells.

10. The semiconductor device according to claim 9, wherein each of the plurality of memory cells comprises a magnetoresistive element and transistor.

11. The semiconductor device according to claim 10, further comprising first and second write buffers which drive opposite ends of the data line to pass a write current.

12. The semiconductor device according to claim 11, wherein the first and second write buffers drive the data line, only when the memory cell on the data line is subjected to inverting/writing.

13. The semiconductor device according to claim 9, wherein each of the plurality of memory cells comprises a phase change resistance element and transistor.

14. A semiconductor device comprising:

a memory array including a plurality of memory cells disposed in desired intersections of a plurality of word lines with a plurality of data lines; and

first and second write buffers which drive opposite ends of the data line to pass a write current,

wherein each of the plurality of memory cells comprises a magnetoresistive element and transistor, and

the first and second write buffers pass the write current, only when the memory cell on the data line is subjected to inverting/writing.

15. The semiconductor device according to claim 14, further comprising:

a sense amplifier disposed in the plurality of data lines to detect a signal read from the memory cell,

wherein the first write buffer drives the data line in response to an output of the sense amplifier, and

the second write buffer drives the data line in response to input data.

16. A semiconductor device comprising:

a memory array comprising a plurality of memory cells disposed in desired intersections of a plurality of word lines with a plurality of data lines; and

a write buffer which drives opposite ends of the data line to pass a write current,

wherein each of the plurality of memory cells comprises a phase change resistance element and transistor, and

the write buffer drives the data line, only when the memory cell on the data line is subjected to inverting/writing.

17. The semiconductor device according to claim 16, further comprising:

a sense amplifier disposed in the plurality of data lines to detect a signal read from the memory cell; and

a comparison circuit which compares an output of the sense amplifier with input data,

wherein the comparison circuit controls the write buffer.

18. The semiconductor device according to claim 17, wherein the comparison circuit comprises an exclusive OR gate.

19. A semiconductor device comprising a memory array comprising a plurality of memory cells,

wherein writing into a plurality of memory cells selected from the plurality of memory cells comprises:

an operation of comparing read data from the plurality of selected memory cells with write data inputted from the outside;

an operation determining logic of the write data as a flag bit based on the comparison result so that the number of bits to be inverted is reduced in the read data; and

an operation of writing the write data decoded in accordance with logic of the flag bit and the flag bit into the plurality of selected memory cells.

20. The semiconductor device according to claim 19, wherein reading from a plurality of memory cells selected from the plurality of memory cells comprises:

an operation of decoding and outputting the data read in response to the flag bit stored in one of the plurality of selected memory cells.