Method and circuit for reducing DRAM refresh power by reducing access transistor sub threshold leakage
First Claim
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1. A memory array, comprising:
- a plurality of memory cells arranged in rows and columns, each of the memory cells including a memory cell capacitor and an access transistor coupled to the memory cell capacitor;
a digit line for each column of memory cells in the memory array, each digit line being coupled to a plurality of access transistors in a respective column of memory cells;
a word line for each row of memory cells in the memory array, each word line being coupled to the gates of a plurality of access transistors in a respective row of memory cells;
a sense amplifier for each column of memory cells, each sense amplifier being coupled to the digit line for a respective column of memory cells, each sense amplifier having a power input and being operable to couple a supply voltage applied to the power input to the digit line to which it is coupled responsive to sensing a predetermined voltage level on the digit line; and
a voltage regulator coupled to the power input of the sense amplifiers for a plurality of columns of memory cells, the voltage regulator having at least one bipolar transistor coupled to the power inputs of the sense amplifiers, the voltage regulator being operable to generate the supply voltage and to regulate the magnitude of the supply voltage responsive to variations in current coupled from the voltage regulator to the sense amplifiers.
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Abstract
The required refresh rate of a DRAM is reduced by biasing active digit lines to a slight positive voltage to reduce the sub threshold current leakage of access transistors in memory cells that are not being accessed. The slight positive voltage is provided by a voltage regulator circuit using one or more bipolar transistors fabricated in a well that electrically isolates the bipolar transistors from the remainder of the substrate. The voltage provided by the voltage regulator is preferably coupled to the access transistors by powering each of the n-sense amplifiers in the DRAM with the voltage from the voltage regulator.
40 Citations
93 Claims
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1. A memory array, comprising:
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a plurality of memory cells arranged in rows and columns, each of the memory cells including a memory cell capacitor and an access transistor coupled to the memory cell capacitor;
a digit line for each column of memory cells in the memory array, each digit line being coupled to a plurality of access transistors in a respective column of memory cells;
a word line for each row of memory cells in the memory array, each word line being coupled to the gates of a plurality of access transistors in a respective row of memory cells;
a sense amplifier for each column of memory cells, each sense amplifier being coupled to the digit line for a respective column of memory cells, each sense amplifier having a power input and being operable to couple a supply voltage applied to the power input to the digit line to which it is coupled responsive to sensing a predetermined voltage level on the digit line; and
a voltage regulator coupled to the power input of the sense amplifiers for a plurality of columns of memory cells, the voltage regulator having at least one bipolar transistor coupled to the power inputs of the sense amplifiers, the voltage regulator being operable to generate the supply voltage and to regulate the magnitude of the supply voltage responsive to variations in current coupled from the voltage regulator to the sense amplifiers. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A semiconductor structure and circuit fabricated in a semiconductor substrate, comprising:
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a well fabricated in the substrate in a manner that electrically isolates the well from the substrate outside of the well;
a memory array fabricated in the semiconductor substrate outside of the well, the memory array including a plurality of memory cells arranged in rows and columns, each of the memory cells comprising a memory cell capacitor and an access transistor coupled to the memory cell capacitor;
a sense amplifiers for each column of memory cells in the memory array, the sense amplifiers being fabricated in the semiconductor substrate outside of the well, each of the sense amplifiers having a power terminal and an output terminal coupled to a plurality of access transistors in a respective column; and
a voltage regulator circuit having an output terminal coupled to the power terminals of a plurality of the sense amplifiers, the voltage regulator circuit including a bipolar transistor fabricated in the isolated well. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
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39. A dynamic random access memory (“
- DRAM”
), comprising;
a command decoder receiving memory command signals through externally accessible command input terminals, the command decoder generating memory control signals responsive to predetermined combinations of the command signals;
an address decoder receiving address signals through externally accessible address input terminals, the address decoder generating row and column addressing signals responsive to the address signals;
a memory array from which data are read and to which data are written at locations corresponding the address signals responsive to the memory control signals, the memory array comprising;
a plurality of memory cells arranged in rows and columns, each of the memory cells including a memory cell capacitor and an access transistor coupled to the memory cell capacitor;
a digit line for each column of memory cells, each digit line being coupled to a plurality of access transistors in a respective column of memory cells;
a word line for each row of memory cells, each word line being coupled to the gates of a plurality of access transistors in a respective row of memory cells;
a sense amplifier for each column of memory cells, each sense amplifier being coupled to the digit line for a respective column of memory cells, each sense amplifier having a power input and being operable to couple a supply voltage applied to the power input to the digit line to which it is coupled responsive to sensing a predetermined voltage level on the digit line;
a data path extending between a plurality of externally accessible data bus terminals and the memory array for coupling data signals to and from the memory array; and
a voltage regulator coupled to the power input of the sense amplifiers for a plurality of columns of memory cells, the voltage regulator having at least one bipolar transistor coupled to the power inputs of the sense amplifiers, the voltage regulator being operable to generate the supply voltage and to regulate the magnitude of the supply voltage responsive to variations in current coupled from the voltage regulator to the sense amplifiers. - View Dependent Claims (40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61)
- DRAM”
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62. A computer system, comprising:
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an integrated circuit processor having a plurality of externally accessible terminals coupled to a processor bus;
an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;
an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system; and
a dynamic random access memory coupled to a processor bus, the dynamic random access memory comprising;
a command decoder receiving memory command signals through externally accessible command input terminals, the command decoder generating memory control signals responsive to predetermined combinations of the command signals;
an address decoder receiving address signals through externally accessible address input terminals, the address decoder generating row and column addressing signals responsive to the address signals;
a memory array from which data are read and to which data are written at locations corresponding the address signals responsive to the memory control signals, the memory array comprising;
a plurality of memory cells arranged in rows and columns, each of the memory cells including a memory cell capacitor and an access transistor coupled to the memory cell capacitor;
a digit line for each column of memory cells, each digit line being coupled to a plurality of access transistors in a respective column of memory cells;
a word line for each row of memory cells, each word line being coupled to the gates of a plurality of access transistors in a respective row of memory cells;
a sense amplifier for each column of memory cells, each sense amplifier being coupled to the digit line for a respective column of memory cells, each sense amplifier having a power input and being operable to couple a supply voltage applied to the power input to the digit line to which it is coupled responsive to sensing a predetermined voltage level on the digit line;
a data path extending between a plurality of externally accessible data bus terminals and the memory array for coupling data signals to and from the memory array; and
a voltage regulator coupled to the power input of the sense amplifiers for a plurality of columns of memory cells, the voltage regulator having at least one bipolar transistor coupled to the power inputs of the sense amplifiers, the voltage regulator being operable to generate the supply voltage and to regulate the magnitude of the supply voltage responsive to variations in current coupled from the voltage regulator to the sense amplifiers. - View Dependent Claims (63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84)
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85. A method of reducing the sub threshold leakage of access transistors in a dynamic random access memory (“
- DRAM”
) fabricated in a semiconductor substrate, comprising;
fabricating a well in the semiconductor substrate in a manner that electrically isolates the well from the substrate;
fabricating at least one bipolar transistor in the well, the at least one bipolar transistor being part of a voltage regulator circuit that generates a regulated output voltage; and
coupling the regulated output voltage to the access transistors. - View Dependent Claims (86, 87, 88, 89, 90, 91, 92, 93)
- DRAM”
Specification