Methods for making a dielectric stack in an integrated circuit

• US 20040043557A1
• Filed: 09/02/2003
• Published: 03/04/2004
• Est. Priority Date: 10/10/2000
• Status: Active Grant

• Current Assignee: ASM International NV
• Original Assignee: ASM International NV
• Inventors: Tuominen, Marko, Skarp, Jarmo, Haukka, Suvi P.
• Granted Patent: US 7,038,284 B2
• Time in Patent Office: Days
• US Class Current: 438/240
• CPC Class Codes: C23C 16/40 Oxides
• CPC Class Codes: C23C 16/403 of aluminium, magnesium or beryllium
• CPC Class Codes: C23C 16/45529 specially adapted for making a layer stack of alternating different compositions or gradient compositions
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02189 the material containing zirconium, e.g. ZrO2
• CPC Class Codes: H01L 21/02192 the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/02299 pre-treatment
• CPC Class Codes: H01L 21/3142 of nano-laminates, e.g. alternating layers of Al203-Hf02
• CPC Class Codes: H01L 21/31604 Deposition from a gas or vapour H01L21/31691, H01L21/31695 take precedence
• CPC Class Codes: H01L 21/3162 on a silicon body
• CPC Class Codes: H01L 28/56 the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: Y10S 977/891 Vapor phase deposition

Abstract

An ultrathin aluminum oxide and lanthanide layers, particularly formed by an atomic layer deposition (ALD) type process, serve as interface layers between two or more materials. The interface layers can prevent oxidation of a substrate and can prevent diffusion of molecules between the materials. In the illustrated embodiments, a high-k dielectric material is sandwiched between two layers of aluminum oxide or lanthanide oxide in the formation of a transistor gate dielectric or a memory cell dielectric. Aluminum oxides can serve as a nucleation layer with less than a full monolayer of aluminum oxide. One monolayer or greater can also serve as a diffusion barrier, protecting the substrate from oxidation and the high-k dielectric from impurity diffusion. Nanolaminates can be formed with multiple alternating interface layers and high-k layers, where intermediate interface layers can break up the crystal structure of the high-k materials and lower leakage levels.

Claims

1. An integrated circuit comprising an interface layer between a conductive material and a dielectric material, the interface layer selected from the group consisting of aluminum oxide and lanthanide oxides and having a thickness less than or equal to about 4 molecular monolayers.

2. The integrated circuit of claim 1, wherein the conductive material comprises silicon.

3. The integrated circuit of claim 1, wherein the conductive material is a single-crystal silicon structure.

4. The integrated circuit of claim 1, wherein the conductive material is a silicon-germanium alloy.

5. The integrated circuit of claim 1, wherein the dielectric material is characterized by a dielectric constant greater than about 10.

6. The integrated circuit of claim 5, further comprising a second interface layer directly contacting an opposite side of the dielectric material, and a second conductive material directly over the second interface layer, the second interface layer selected from the group consisting of aluminum oxide and lanthanide oxides and having a thickness of less than or equal to about 4 molecular monolayers.

7. The integrated circuit of claim 6, wherein the conductive material comprises a silicon substrate, wherein the second conductive material comprises a gate electrode, and wherein the interface layer, dielectric material and second interface layer form a gate dielectric for an integrated transistor.

8. The integrated circuit of claim 6, wherein the conductive material comprises a storage electrode in a memory cell, and the second conductive material comprises a reference electrode, wherein the interface layer, dielectric material and second interface layer form a capacitor dielectric for an integrated capacitor.

9. The integrated circuit of claim 5, wherein the interface layer has a thickness between about 3 Å

and 15 Å

.

10. The integrated circuit of claim 9, wherein the interface layer has a thickness between about 3 Å

and 9 Å

.

11. The integrated circuit of claim 1, further comprising a plurality of alternating interface and dielectric layers, each interface layer selected from the group consisting of aluminum oxide and lanthanide oxides and having a thickness between about 1 Å

and 15 Å

, each dielectric layer having a dielectric constant of greater than about 5.

12. The integrated circuit of claim 11, wherein each interface layer comprises aluminum oxide and each dielectric layer comprises zirconium oxide.