Integrated GPS receiver architecture

• US 20040043745A1
• Filed: 08/30/2002
• Published: 03/04/2004
• Est. Priority Date: 08/30/2002
• Status: Abandoned Application

• Current Assignee: Jackie Balodis, Miroslaw Balodis, Richard Keegan, Richard Najarian
• Original Assignee: Jackie Balodis, Miroslaw Balodis, Richard Keegan, Richard Najarian
• Inventors: Balodis, Miroslaw, Balodis, Jackie, Keegan, Richard, Najarian, Richard
• Application Number:
  US10/233,056
• Publication Number:
  US 20040043745A1
• Time in Patent Office: Days
• US Class Current: 455/334
• CPC Class Codes: G01S 19/21 Interference related issues ; Issues related to cross-correlation, spoofing or other methods of denial of service
• CPC Class Codes: G01S 19/32 Multimode operation in a single same satellite system, e.g. GPS L1/L2
• CPC Class Codes: G01S 19/36 relating to the receiver frond end
• CPC Class Codes: H04B 1/30 for homodyne or synchrodyne receivers demodulator circuits H03D1/22

Abstract

The present invention relates to a single semiconductor die having an integrated low noise amplifier, a radio frequency (RF) subsystem, and sampling circuitry for use in a GPS receiver. The low noise amplifier has electrical performance suitable to receive a GPS signal from a unity gain antenna, thereby eliminating the need for external gain or an active antenna. After being amplified, the GPS signal is processed by a RF subsystem such that the signal is filtered and downconverted to a baseband signal, and the baseband signal is digitized by the sampling circuitry.

Claims

1. A semiconductor die comprising:

a low noise amplifier adapted to receive a GPS input signal from a passive GPS antenna and produce an amplified GPS signal;

a RF subsystem operatively associated with said low noise amplifier and adapted to down-convert and filter said amplified GPS signal; and

sampling circuitry operatively associated with said RF subsystem and adapted to provide a digitized output signal including GPS information carried in said GPS input signal,

said low noise amplifier, said RF subsystem, and said sampling circuitry formed on a single semiconductor die.

2. The semiconductor die according to claim 1 wherein said RF subsystem is further adapted to amplify said amplified GPS signal and control amplification of said amplified GPS signal such that a signal-to-noise ratio of said digitized output signal is maximized.

3. The semiconductor die according to claim 1 wherein said RF subsystem comprises downconversion circuitry operatively associated with said low noise amplifier and adapted to receive a first synthesizer output signal and produce an IF signal from said amplified GPS input signal.

4. The semiconductor die according to claim 3 wherein said RF subsystem further comprises a frequency synthesizer operatively associated with said downconversion circuitry and adapted to produce said first synthesizer output signal.

5. The semiconductor die according to claim 4 wherein said frequency synthesizer comprises a first divider circuit adapted to divide said first synthesizer output signal to provide a second synthesizer output signal to said sampling circuitry.

6. The semiconductor die according to claim 5 wherein said frequency synthesizer further comprises a frequency and phase detector having first and second inputs and a second divider circuit adapted to divide said second synthesizer output signal to provide a first input signal to said first input and wherein said second input is operatively connected to a reference oscillator to receive a reference signal.

7. The semiconductor die according to claim 6 wherein said frequency synthesizer further comprises a VCO adapted to provide said first synthesizer output signal in response to an output of said frequency and phase detector.

8. The semiconductor die according to claim 7 wherein said frequency synthesizer further includes a filter operatively coupling said frequency and phase detector to said VCO and adapted to filter the first synthesizer output signal provided to said VCO.

9. The semiconductor die according to claim 3 further comprising a first external connection for external filtering circuitry operatively associated between said low noise amplifier and said downconversion circuitry, wherein said external filtering circuitry is adapted to remove unwanted frequency components from said amplified GPS input signal.

10. The semiconductor die according to claim 3 further comprising a second external connection for an external SAW filter operatively associated between said downconversion circuitry and said sampling circuitry, wherein said external SAW filter is adapted to remove unwanted frequency components from said IF signal.

11. The semiconductor die according to claim 10 further comprising first gain logic operatively associated between said downconversion circuitry and said second external connection and second gain logic operatively associated between said second external connection and said sampling circuitry, wherein said first gain logic is adapted to amplify said IF signal and provide said SAW filter with a signal having sufficient input power and said second gain logic is adapted to provide said sampling circuitry with a filtered signal having sufficient input power.

12. The semiconductor die according to claim 1 wherein said sampling circuitry comprises an analog-to-digital converter.

13. The semiconductor die according to claim 3 wherein said downconversion circuitry comprises a mixer.

14. The semiconductor die according to claim 3 wherein said downconversion circuitry comprises a mixer and said sampling circuitry comprises an analog-to-digital converter.

15. The semiconductor die according to claim 3 wherein said downconversion circuitry and said sampling circuitry are adapted to receive differential signals.

16. The semiconductor die according to claim 1 wherein said semiconductor die is fabricated in a SiGe semiconductor process.

17. A semiconductor die fabricated in a SiGe semiconductor process comprising:

a low noise amplifier adapted to receive a GPS input signal from a unity gain antenna and produce an amplified GPS signal;

a RF subsystem operatively associated with said low noise amplifier and adapted to downconvert and filter said amplified GPS signal; and

sampling circuitry operatively associated with said RF subsystem adapted to provide a digitized output signal including GPS information carried in said GPS input signal,

said low noise amplifier, said RF subsystem, and said sampling circuitry formed on a single semiconductor die fabricated in a SiGe semiconductor process.

18. The semiconductor die according to claim 17 wherein said RF subsystem is further adapted to amplify said amplified GPS signal and control amplification of said amplified GPS signal such that a signal-to-noise ratio of said digitized output signal is maximized.

19. The semiconductor die according to claim 17 wherein said RF subsystem comprises downconversion circuitry operatively associated with said low noise amplifier and adapted to receive a first synthesizer output signal and produce an IF signal from said amplified GPS input signal.

20. The semiconductor die according to claim 19 wherein said RF subsystem further comprises a frequency synthesizer operatively associated with said downconversion circuitry and adapted to produce said first synthesizer output signal.

21. The semiconductor die according to claim 20 wherein said frequency synthesizer comprises a first divider circuit adapted to divide said first synthesizer output signal to provide a second synthesizer output signal to said sampling circuitry.

22. The semiconductor die according to claim 21 wherein said frequency synthesizer further comprises a frequency and phase detector having first and second inputs and a second divider circuit adapted to divide said second synthesizer output signal to provide a first input signal to said first input and wherein said second input is operatively connected to a reference oscillator to receive a reference signal.

23. The semiconductor die according to claim 22 wherein said frequency synthesizer further comprises a VCO adapted to provide said first synthesizer output signal in response to an output of said frequency and phase detector.

24. The semiconductor die according to claim 23 wherein said frequency synthesizer further includes a filter operatively coupling said frequency and phase detector to said VCO and adapted to filter the first synthesizer output signal provided to said VCO.