Multiple test bench optimizer

• US 20040044509A1
• Filed: 04/26/2001
• Published: 03/04/2004
• Est. Priority Date: 04/28/2000
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Demler, Michael J., Ellis, Geoffrey, Lim, Stephen
• Granted Patent: US 7,191,112 B2
• Time in Patent Office: Days
• US Class Current: 703/14
• CPC Class Codes: G06F 30/36 Circuit design at the analogue level
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

Test benches, simulations, and scripts are invoked in parallel for testing multiple points in a circuit being synthesized in an Analog Mixed Signal environment. A simulation system for simultaneously optimizing performance characteristics in circuit synthesis uses a set of design parameters. At least one circuit model is used to incorporate the set of design parameters, each circuit model adapted to model a portion of the circuit pertaining to a performance characteristic. At least one analysis test bench is then connected to each circuit model. Each analysis test bench is adapted to model circuitry external to the circuit and control the type of analysis to be performed for each performance characteristic of the circuit.

Claims

1. A method of simultaneously optimizing performance characteristics in circuit synthesis, comprising the steps of:

(a) generating a set of circuit parameters for each performance characteristic of a circuit;

(b) simultaneously passing each said set of circuit parameters through a respective circuit model; and

(c) running a simulation of each said circuit model on an analysis test bench in order to measure performance of said circuit model using said set of circuit parameters, each said analysis test bench adapted to model circuitry external to said circuit and control the type of analysis to be performed for each said performance characteristic of said circuit.

2. A method according to claim 1, further comprising the step of receiving the measurements of performance for each simulation in an optimizer, said optimizer adapted to determine whether specifications were met for said simulation.

3. A method according to claim 2, further comprising the step of generating new set of circuit parameter values in said optimizer.

4. A method according to claim 3, further comprising the step of passing said new set of circuit parameter values through the respective said circuit model.

5. A method according to claim 1, further comprising the step of assigning each said analysis to a separate processor for parallel processing.

6. A method according to claim 1, further comprising the step of checking a lookup database for previously optimized performance characteristics.

7. A method according to claim 1, further comprising the step of saving optimized performance characteristics to a lookup database.

8. A method according to claim 1, further comprising the step of setting up ranges for each said analysis test bench and providing design parameters using a simulation script.

9. A method according to claim 1, further comprising the step of mapping the function of a design parameter to a performance characteristic.

10. A simulation system for simultaneously optimizing performance characteristics in circuit synthesis, comprising:

(a) a set of design parameters for a circuit;

(b) at least one circuit model for incorporating said set of design parameters, each said circuit model adapted to model a portion of said circuit pertaining to a performance characteristic; and

(c) at least one analysis test bench connected to each said circuit model, each said analysis test bench adapted to model circuitry external to said circuit and control the type of analysis to be performed for each said performance characteristic of said circuit.

11. A simulation system according to claim 10 additionally comprising an optimizer adapted to collect the results of said analysis of each said analysis test bench and compare said results to optimal performance specifications for said circuit.

12. A simulation system according to claim 11, wherein said optimizer comprises an optimization algorithm.

13. A simulation system according to claim 12, wherein said optimization algorithm is adapted to generate parameter values to be passed to each said analysis test bench.

14. A simulation system according to claim 10, further comprising a simulator for each said analysis test bench.

15. A simulation system according to claim 10, wherein each said analysis test bench is adapted to run multiple occurrences of said analysis for each said circuit.

16. A simulation system according to claim 10, wherein said analysis may be performed over multiple operating conditions.

17. A simulation system according to claim 16, wherein said multiple operating conditions are selected from the group consisting of temperature, supply voltage, and fabrication process.

18. A simulation system according to claim 10, wherein said circuitry is selected from the group consisting of stimuli, power supplies, and load devices.

19. A simulation system according to claim 10, further comprising a processor for each said circuit model.

20. A simulation system according to claim 10, further comprising at least one simulation script for each said circuit model.

21. A simulation system according to claim 10, further comprising a synthesis plan adapted to set out rules for said analysis.

22. A simulation system according to claim 10, further comprising a lookup database.

23. A simulation system according to claim 22, wherein said lookup database includes a set of performance specifications for each said circuit model.

24. A simulation system according to claim 10, wherein said design parameters are selected from the group consisting of transistor dimensions, bias current values, and adjustable circuit parameters.