Addressing scheme supporting variable local addressing and variable global addressing

• US 20040044806A1
• Filed: 05/15/2003
• Published: 03/04/2004
• Est. Priority Date: 05/15/2002
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Kelly, James D., Rowlands, Joseph B., Moll, Laurent R., Gulati, Manu, Oner, Koray
• Granted Patent: US 6,941,440 B2
• Time in Patent Office: Days
• US Class Current: 710/3
• CPC Class Codes: G06F 13/1684 using multiple buses

Abstract

A node comprises at least one agent and an input/output (I/O) circuit coupled to an interconnect within the node. The I/O circuit is configured to communicate on a global interconnect to which one or more other nodes are coupled during use. Addresses transmitted on the interconnect are in a first local address space of the node, and addresses transmitted on the global interconnect are in a global address space. The first local address space includes at least a first region used to address at least a first resource of the node. The node is programmable, during use, to relocate the first region within the first local address space, whereby a same numerical value in the first local address space and a second local address space corresponding to one of the other nodes coupled to the global interconnect refers to the first resource in the node during use.

Claims

1. A node comprising:

at least one agent and an input/output (I/O) circuit coupled to an interconnect within the node to communicate between the agent and the I/O circuit, wherein the I/O circuit is configured to communicate on a global interconnect to which one or more other nodes are coupled during use, and wherein addresses transmitted on the interconnect are in a first local address space of the node, and wherein addresses transmitted on the global interconnect are in a global address space, and wherein the first local address space includes at least a first region used to address at least a first resource of the node;

wherein the node is programmable, during use, to relocate the first region within the first local address space, whereby a same numerical value in the first local address space and a second local address space corresponding to one of the other nodes coupled to the global interconnect refers to the first resource in the node during use.

2. The node as recited in claim 1 wherein the node is further programmable, during use, to map a corresponding region of the global address space to the first region, whereby a same numerical value in the first local address space and in the global address space refers to the first resource in the node during use.

3. The node as recited in claim 1 wherein the agent comprises a memory controller configured to couple to a memory, and wherein a portion of the memory comprises the first resource.

4. The node as recited in claim 3 wherein the memory controller is programmed, during use, to respond to the first region as relocated in the first local address space.

5. The node as recited in claim 3 wherein the memory controller comprises a coherency resolution pipeline coupled to a memory request queue and coupled to receive an address of a transaction from the interconnect, and wherein the coherency resolution pipeline is configured to translate the address to row and column addresses for the memory prior to storing the transaction in the memory request queue.

6. The node as recited in claim 3 further comprising a packet manager coupled to receive packets and store the packets in the memory and a processor coupled to the interconnect, and wherein the packet manager includes an interrupt timer, and wherein the packet manager is configured to interrupt the processor responsive to an expiration of the interrupt timer.

7. The node as recited in claim 1 wherein the I/O circuit includes one or more local I/O devices addressed by the first region, and wherein the I/O circuit is programmed, during use, to respond to the first region as relocated in the first local address space.

8. The node as recited in claim 1 wherein the first region is one of a plurality of regions in the first local address space, wherein each of the plurality of regions is used to address different resources within the node, and wherein the node is programmable, during use, to relocate each region of the plurality of regions in the first local address space and to map corresponding regions of the global address space to each of the plurality of regions.

9. The node as recited in claim 1 wherein the I/O circuit comprises an overflow buffer configured to capture transmissions on the global interconnect.

10. The node as recited in claim 1 further comprising maintaining internode coherency using a cache-coherent nonuniform memory access scheme.

11. A system comprising:

a global interconnect, wherein addresses transmitted on the global interconnect are included in a global address space;

a first node coupled to the global interconnect, the first node having a first local address space within the first node, the first node comprising at least one resource addressed using a first region within the first local address space; and

a second node coupled to the global interconnect, the second node having a second local address space within the second node;

wherein the first node is programmable, during use, to relocate the first region within the first local address space, and wherein the second node is programmable, during use, to relocate regions within the second local address space to map a second region within the second local address space for transmission on the global interconnect, the second region comprising addresses having the same numerical value as addresses in the first region, whereby the resource in the first node is accessed using a same numerical value of the address in the first local address space and the second local address space during use.

12. The system as recited in claim 11 wherein the first node is further programmable, during use, to map a corresponding region of addresses from the global interconnect to the first region of addresses.

13. The system as recited in claim 12 wherein a first agent in the second node is configured to generate a first transaction having a first address in the second region to access the location, and wherein the second node is configured to generate a global transaction on the global interconnect in response to the first address, the global transaction including a second address in the global address space and equal in value to the first address.

14. The system as recited in claim 13 wherein the second address is in the corresponding region of the global address space, and is mapped by the first node to a third address in the local address space that is equal in value to the first address.

15. The system as recited in claim 11 wherein a first agent in the first node is configured to generate a first transaction having a first address in the first region to access the resource, and wherein a second agent in the second node is configured to generate a transaction having a second address in the second region, and wherein the first address and the second address are numerically equal.

16. The system as recited in claim 11 wherein the first node comprises a memory controller configured to couple to a memory, and wherein a portion of the memory comprises the first resource.

17. The system as recited in claim 16 wherein the memory controller is programmed, during use, to respond to the first region as relocated in the first local address space.

18. The system as recited in claim 11 wherein the first node includes one or more local I/O devices addressed by the first region, and wherein the first node is programmed, during use, to respond to the first region as relocated in the first local address space.

19. The system as recited in claim 11 wherein the first region is one of a plurality of regions in the first local address space, wherein each of the plurality of regions is used to address different resources within the first node, and wherein the first node is programmable, during use, to relocate each of the plurality of regions in the first local address space.

20. A method comprising:

configuring a first node to map a first region of a global address space to a second region of a first local address space within the first node, the second region defined to address at least one resource in the first node; and

programming the first node to relocate the second region within the first local address space, whereby a same numerical value is used in the first local address space and in the global address space to address a location in the first region.

21. The method as recited in claim 20 wherein configuring the first node comprises programming a global address to local address map storage in the first node to map the second region to the first region.

22. The method as recited in claim 20 further comprising programming a second node to map one or more regions in a second local address space of the second node such that a third region having a same numerical value as the second region and the first region is mapped to the global address space.