System and method for optimizing interconnections of memory devices in a multichip module

• US 20040044833A1
• Filed: 08/29/2002
• Published: 03/04/2004
• Est. Priority Date: 08/29/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ryan, Kevin J.
• Granted Patent: US 7,836,252 B2
• Time in Patent Office: Days
• US Class Current: 711/5
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

Abstract

An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have the same propagation time regardless of which device is involved. The hub receives memory signals from a controller over a high speed data link which the hub translates into electrical data, command and address signals. These signals are applied to the memory devices over busses having equivalent path lengths. The busses may also be used by the memory devices to apply data signals to the memory hub. Such data signals can be converted by the memory hub into memory signals and applied to the controller over the high speed data link. In one example, the memory hub is located in the center of the memory module.

Claims

1. A memory module comprising;

a circuit board;

a memory hub on the circuit board operable to receive memory signals from a high speed memory link and apply memory signals on the high speed memory link, the memory signals comprising at least one of command, address or data signals, the memory hub being further operable to translate between memory signals and electrical command, address and data signals;

a plurality of memory devices on the circuit board, the memory devices being located substantially equidistant from the memory hub and being electrically coupled directly to the memory hub to receive command, address and data signals from the memory hub and to provide data signals to the memory hub; and

electrical contacts on the circuit board connected to power terminals of the memory devices and the memory hub.

2. The module of claim 1 wherein the high speed memory link comprises at least one of a high speed control bus operable to transmit command signals, a high speed address bus operable to transmit address signals and a high speed data bus operable to transmit data signals.

3. The module of claim 2 wherein the high speed memory link further comprises at least one point-to-point link.

4. The module of claim 3 wherein any of the busses and point-to-point links may be multiplexed.

5. The module of claim 1 wherein the high speed memory link comprises at least one point-to-point link.

6. The module of claim 1 wherein the high speed memory link comprises at least one unidirectional high speed link operable to transmit at least one of command, address and write data signals from a controller to the memory hub.

7. The module of claim 1 wherein the high speed memory link comprises at least one unidirectional high speed link operable to transmit at least one of command and read data signals from the memory hub to the controller.

8. The module of claim 1, further comprising a high speed hub communication link operable to transmit at least one of command, address and data signals between the memory hub and a second memory hub.

9. The module of claim 1 wherein the high speed memory link comprises an optical bus and the memory signals are optical signals, and further wherein the memory hub includes at least one optical transmitter operable to send memory signals and at least one optical receiver operable to receive memory signals, the memory hub being further operable to translate between the optical memory signals and the electrical command, address and data signals.

10. The module of claim 9 wherein the high speed memory link comprises a fiber optic link.

11. The module of claim 9 wherein the high speed memory link comprises free space.

12. The module of claim 9 wherein the memory module is a DIMM.

13. The module of claim 9 wherein the plurality of memory devices comprise DRAM devices.

14. The module of claim 9 wherein each memory device is electrically coupled to the memory hub by a control bus, an address bus and a data bus.

15. The module of claim 9 wherein the memory hub applies the command, address and data signals to each memory device simultaneously.

16. The module of claim 9 wherein the memory hub detects address information in a memory signal and applies command, address and data signals to a corresponding memory device.

17. The module of claim 9 wherein the memory hub is positioned at a center of the module.

18. A memory module comprising;

a circuit board;

a memory hub on the circuit board, the memory hub being adapted to receive memory signals from a high speed memory link and including at least one communications port, the hub being operable to develop address, data and command signals responsive to the received memory signals, and being operable to apply memory signals on the high speed memory link responsive to data signals received at each communications port;

a plurality of memory devices on the circuit board, each memory device being electrically coupled to a respective port on the memory hub through a corresponding memory bus, and each memory bus having substantially the same electrical characteristics; and

electrical contacts on the circuit board connected to power terminals of the memory devices and the memory hub.

19. The module of claim 18 wherein the high speed memory link comprises at least one of a high speed control bus operable to transmit command signals, a high speed address bus operable to transmit address signals and a high speed data bus operable to transmit data signals.

20. The module of claim 19 wherein the high speed memory link further comprises at least one point-to-point link.

21. The module of claim 20 wherein any of the busses and point-to-point links may be multiplexed.

22. The module of claim 18 wherein the high speed memory link comprises at least one point-to-point link.

23. The module of claim 18 wherein the high speed memory link comprises at least one unidirectional high speed link operable to transmit at least one of command, address and write data signals from a controller to the memory hub.

24. The module of claim 18 wherein the high speed memory link comprises at least one unidirectional high speed link operable to transmit at least one of command and read data signals from the memory hub to the controller.

25. The module of claim 18, further comprising a high speed hub communication link operable to transmit at least one of command, address and data signals between the memory hub and a second memory hub.

26. The module of claim 18 wherein the high speed memory link comprises an optical bus, and further wherein the memory hub includes at least one optical transmitter operable to send memory signals and at least one optical receiver operable to receive memory signals, the memory hub being further operable to translate between the optical memory signals and the electrical command, address and data signals.

27. The module of claim 26 wherein the high speed memory link comprises a fiber optic link.

28. The module of claim 26 wherein the high speed memory link comprises free space.

29. The module of claim 26 wherein the memory module comprises a DIMM.

30. The module of claim 26 wherein the plurality of memory devices comprise DRAM devices.

31. The module of claim 26 wherein each memory bus comprises control bus, address and data busses.

32. The module of claim 26 wherein the memory hub applies the command, address and data signals to each memory device simultaneously.

33. The module of claim 26 wherein the memory hub detects address information in a memory signal and applies command, address and data signals to a corresponding memory device.

34. The module of claim 26 wherein the memory hub is positioned at a center of the module.

35. A computer system, comprising:

a data input device;

a data output device;

a processor coupled to the data input and data output devices;

a controller electrically coupled to the processor, the controller being operable to receive and transmit memory signals on a high speed memory link;

a memory module comprising;

a memory hub coupled to the high speed link, the memory hub having electrical output ports for sending and receiving electrical signals, the memory hub being operable to translate received electrical signals to corresponding memory signals to be applied to the high speed memory link and translate memory signals into corresponding electrical signals to be applied at the output ports; and

a plurality of memory devices on the circuit board, with each memory device being located substantially equidistant from the memory hub and being electrically coupled directly to a respective output port of the memory hub to receive command, address and data signals from the memory hub and to provide data signals to the memory hub; and

electrical contacts connected to power terminals of the memory devices and the memory hub.

36. The module of claim 35 wherein the high speed memory link comprises at least one of a high speed control bus operable to transmit command signals, a high speed address bus operable to transmit address signals and a high speed data bus operable to transmit data signals.

37. The module of claim 36 wherein the high speed memory link further comprises at least one point-to-point link.

38. The module of claim 37 wherein any of the busses and point-to-point links may be multiplexed.

39. The module of claim 35 wherein the high speed memory link comprises at least one point-to-point link.

40. The module of claim 35 wherein the high speed memory link comprises at least one unidirectional high speed link operable to transmit at least one of command, address and write data signals from a controller to the memory hub.

41. The module of claim 36 wherein the high speed memory link comprises at least one unidirectional high speed link operable to transmit at least one of command and read data signals from the memory hub to the controller.

42. The module of claim 36, further comprising a high speed hub communication link operable to transmit at least one of command, address and data signals between the memory hub and a second memory hub.

43. The computer system of claim 35 wherein the high speed memory link comprises an optical bus, and further wherein the memory hub includes at least one optical transmitter operable to send memory signals and at least one optical receiver operable to receive memory signals, the memory hub being further operable to translate between the optical memory signals and the electrical signals;

and further wherein the controller is operable to receive electrical signals from the processor and generate corresponding memory signals with at least one optical transmitter, the controller being further operable to receive memory signals with at least one optical receiver and generate corresponding electrical signals.

44. The computer system of claim 43 wherein the high speed memory link comprises a fiber optic link.

45. The computer system of claim 43 wherein the high speed memory link comprises free space.

46. The computer system of claim 43 wherein the memory module comprises a DIMM.

47. The computer system of claim 43 wherein the plurality of memory devices comprise DRAM devices.

48. The computer system of claim 43 wherein each memory device is electrically coupled to the memory hub through control, address bus and data busses.

49. The computer system of claim 43 wherein the memory hub applies command, address and data signals to each memory device simultaneously.

50. The computer system of claim 43 wherein the memory hub detects address information in a memory signal and applies command, address and data signals to a corresponding memory device.

51. The module of claim 43 wherein the memory hub is positioned at a center of the module.

52. A method of communicating between a memory device on a memory module and a controller, comprising:

transmitting a first memory signal from the controller to a memory hub located on the module;

receiving the first memory signal in the memory hub;

converting the first memory signal to a first device signal in the memory hub;

transmitting the first device signal directly from the memory hub to a memory device over an electrical conductor having a first length;

transmitting a second memory signal from the controller to the memory hub;

receiving the second memory signal in the memory hub;

converting the second memory signal to a second device signal in the memory hub;

transmitting the second device signal directly from the memory hub to a second memory device over an electrical conductor having the first length.

53. The method according to claim 52 wherein transmitting a first memory signal from the controller to a memory hub located on the module and transmitting a second memory signal from the controller to the memory hub comprise applying first and second memory signals to at least one of a high speed control bus, a high speed address bus and a high speed data bus.

54. The method according to claim 52 wherein transmitting a first memory signal from the controller to a memory hub located on the module and transmitting a second memory signal from the controller to the memory hub comprise applying first and second memory signals to at least one point to point link.

55. The method according to claim 54, wherein transmitting a first memory signal from the controller to a memory hub located on the module and transmitting a second memory signal from the controller to the memory hub comprise applying first and second memory signals to at least one of a high speed control bus, a high speed address bus, a high speed data bus and a point to point link.

56. The method according to claim 55 wherein any of the busses and point to point links may be multiplexed.

57. The method according to claim 52 wherein transmitting a first memory signal from the controller to a memory hub located on the module comprises applying the first memory signal to at least one unidirectional high speed link operable to transmit at least one of command, address and write data signals.

58. The method according to claim 52, further comprising transmitting an inter hub signal from the memory hub to a second memory hub.

59. The method according to claim 52 further comprising:

transmitting a data signal from the first memory device over the first length to the memory hub;

converting the data signal to a third memory signal in the memory hub;

transmitting the third memory signal from the memory hub to the controller; and

receiving the third memory signal in the controller.

60. The method according to claim 59 wherein transmitting the third memory signal from memory hub to the controller comprises applying the third memory signal to at least one of a high speed control bus, a high speed address bus and a high speed data bus.

61. The method according to claim 59 wherein transmitting the third memory signal from memory hub to the controller comprises applying the third memory signal to at least one point to point link.

62. The method according to claim 60, wherein transmitting the third memory signal from memory hub to the controller comprises applying the third memory signal to at least one of a high speed control bus, a high speed address bus, a high speed data bus and a point to point link.

63. The method according to claim 62 wherein any of the busses and point to point links may be multiplexed.

64. The method according to claim 52 wherein transmitting the third memory signal from memory hub to the controller comprises applying the third memory signal to at least one unidirectional high speed link operable to transmit at least one of command and read data signals.

65. The method according to claim 52, further comprising transmitting an inter hub signal from the memory hub to a second memory hub.

66. The method according to claim 60 wherein transmitting first and second memory signals over an optical bus comprises transmitting first and second memory signals over a fiber optic link.

67. The method according to claim 60 wherein transmitting first and second memory signals over an optical bus comprises transmitting first and second memory signals through free space.

68. The method according to claim 60 wherein receiving the first and second memory signals in the memory hub comprises receiving the first and second memory signals with at least one optical receiver located on the memory hub.

69. The method according to claim 60 further comprising:

transmitting a data signal from the first memory device over the first length to the memory hub;

converting the data signal to an optical memory signal in the memory hub;

transmitting the optical memory signal from the memory hub to the controller; and

receiving the optical memory signal in the controller.