Automode select

• US 20040044925A1
• Filed: 08/27/2002
• Published: 03/04/2004
• Est. Priority Date: 08/27/2002
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Piper, Stephen, Craton, Dennis, Trembley, Matthew
• Granted Patent: US 7,058,854 B2
• Time in Patent Office: Days
• US Class Current: 714/30
• CPC Class Codes: G06F 11/1417 Boot up procedures
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area

Abstract

A microprocessor based system automatically detects the occurrence of certain conditions in the microprocessor. The conditions may include a determination of data corruption in the microprocessor. If a determination is made that data is corrupted, the microprocessor may be reloaded from a non-volatile memory. During a reload, a microcontroller controls the microprocessor. The non-volatile memory may be a flash memory or non-volatile random access memory.

Claims

1. A method for verifying data validity in a microprocessor, comprising the steps of:

determining data validity in a microprocessor through the state of a first signal by the microprocessor; and

if the microprocessor data is determined invalid because of the state of the first signal, then changing an operational mode of the microprocessor.

2. The method of claim 1, further comprising, if microprocessor data is determined to be invalid, then resetting the microprocessor after the step of changing the operational mode of the microprocessor.

3. The method of claim 1, further comprising, if microprocessor data is determined to be invalid, then resetting the microprocessor before the step of changing the operational mode of the microprocessor.

4. The method of claim 2, wherein the step of changing the operational mode of the microprocessor is performed by a microcontroller.

5. The method of claim 1, further comprising flashing a flash memory after changing an operational mode of the microprocessor.

6. A method for automatically detecting data corruption in a microprocessor, comprising the steps of:

waiting for a local reset signal to become inactive; and

when the local reset signal becomes inactive, determining if a memory valid signal is active; and

if the memory valid signal is not active at the time of determination, then resetting the microprocessor to a different operational mode.

7. The method of claim 6, wherein the step of resetting the microprocessor further comprises the step of determining if a predetermined period of time has expired before resetting the microprocessor.

8. The method of claim 7, wherein, if the predetermined period of time has expired, then providing a bus reset pulse.

9. The method of claim 7, wherein, if the predetermined period of time has expired, then loading the microprocessor from a non-volatile memory.

10. The method of claim 8, wherein the bus reset pulse is a peripheral component interconnect (PCI) bus reset pulse.

11. The method of claim 6, wherein the local reset signal deactivates a microcontroller timer.

12. The method of claim 11, wherein a non-volatile memory is coupled to the microprocessor.

13. The method of claim 12, wherein the non-volatile memory is a flash memory.

14. A system for automatically detecting data corruption in a microprocessor, comprising:

a microprocessor that normally operates in a first mode; and

a microcontroller coupled to the microprocessor, the microcontroller putting the microprocessor in a second mode upon the occurrence of a microprocessor fault condition sensed by the microcontroller.

15. The system of claim 14, wherein the microprocessor provides an indicator signal to the microcontroller.

16. The system of claim 15, wherein the indicator signal is used by the microcontroller to activate a timer.

17. The system of claim 14, further comprising a non-volatile memory coupled to the microprocessor, wherein the non-volatile memory is a flash memory.

18. The system of claim 15, wherein the indicator signal is transmitted from a general purpose input/output pin.

19. The system of claim 14, wherein the microprocessor propagates a system reset signal by transmitting a local reset signal to the microcontroller.

20. The system of claim 15, further comprising a non-volatile memory coupled to the microprocessor, wherein the indicator signal indicates data corruption in the non-volatile memory.

21. The system of claim 14, wherein the system is disposed upon a circuit board.

22. The system of claim 21, wherein operating conditions in the system are indicated by light emitting diodes.

23. The system of claim 14, wherein the microcontroller causes the microprocessor to enter normal mode after boot up.

24. A system for automatically detecting data corruption in a microprocessor, comprising:

a non-volatile memory;

a microprocessor coupled to the non-volatile memory, the microprocessor generating a first signal to indicate a microprocessor data corruption fault state, the microprocessor being in a first mode;

a microcontroller coupled to the microprocessor, the microcontroller receiving the first signal and sending a second signal in response to the first signal, the second signal causing the microprocessor to enter a second mode.

25. The system of claim 24, further comprising at least one light emitting diode to indicate a system fault state.

26. The system of claim 24, wherein the first signal is generated from a dedicated general purpose input/output pin of the microprocessor.

27. The system of claim 24, wherein the second signal represents a microprocessor mode.

28. A system for automatically detecting data corruption in a microprocessor, comprising:

means for generating a fault indicator signal;

means for waiting for the fault indicator signal to indicate a non-fault condition for data and instructions non-volatilely stored in the means for generating a fault indicator signal;

means for resetting the means for generating a fault indicator signal after a predetermined period of time has elapsed; and

means for generating a mode signal for the means for generating a fault indicator signal.

29. The system of claim 28, further comprising means for displaying a fault condition.

30. The system of claim 29, wherein the means for displaying a fault condition is coupled to the means for generating a mode signal.

31. The system of claim 28, wherein the system interfaces with a peripheral component interconnect (PCI) bus.

32. The system of claim 28, wherein the system interfaces with a peripheral component interconnect extended (PCIX) bus.