Memory technology test apparatus

• US 20040044933A1
• Filed: 08/29/2002
• Published: 03/04/2004
• Est. Priority Date: 08/29/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph M.
• Granted Patent: US 7,020,815 B2
• Time in Patent Office: Days
• US Class Current: 714/718
• CPC Class Codes: G11C 2029/5004 Voltage
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

A programmable control device that creates an environment for controlling, testing and evaluating memory designs. The control device provides automated testing of address eyes, data eyes and voltage margins. The control device interfaces with a conventional computer system, such as a personal computer (PC). The computer system gathers test data and outputs the data in a graphical format if desired. Since the control device is quickly re-programmable, new memory sequencing, control, timing and power techniques are rapidly proto-typed in an inexpensive and timely manner.

Claims

1. A programmable control circuit for testing a memory device, said control circuit comprising:

a programmable memory engine, said memory engine generating and outputting requests used to test the memory device;

a memory sequencer electrically connected to said memory engine, said memory sequencer having a first output electrically connected to the memory device, said sequencer using said first output to control the memory device in response to commands received from said memory engine, said memory sequencer having an input for receiving test data from the memory device and a second output for outputting the test data; and

a capture analyzer circuit electrically connected to said memory engine and said second output, said capture analyzer circuit inputting and storing the test data.

2. The control circuit of claim 1 further comprising a host computer interface electrically connected to said memory engine, memory sequencer and said capture analyzer circuit, said host computer interface allowing information and data within said control circuit to be output to a host computer connected to said interface.

3. The control circuit of claim 2, wherein said host computer interface allows said control circuit to input information and data from the host computer.

4. The control circuit of claim 2, wherein said host computer interface is a peripheral component interconnect interface.

5. The control circuit of claim 1 further comprising a configuration and control component for configuring and controlling components within said control circuit.

6. The control circuit of claim 5, wherein said configuration and control component configures and controls delay lines connected to receive a clock signal.

7. The control circuit of claim 5, wherein said configuration and control component configures and controls voltage sources used by the memory device.

8. The control circuit of claim 1 further comprising internal memory arrays connected to said memory engine, wherein said memory engine copies the test data within said capture analyzer circuit to said internal memory arrays.

9. The control circuit of claim 1 further comprising an address buffer electrically connected to said memory engine, said address buffer comprising address test patterns for testing the memory device.

10. The control circuit of claim 1 further comprising a data buffer electrically connected to said memory engine, said data buffer comprising data test patterns for testing the memory device.

11. The control circuit of claim 1, wherein said memory engine is a programmable direct memory access controller.

12. The control circuit of claim 11, wherein said memory engine performs random request spacing.

13. A test circuit board comprising:

a memory device; and

a programmable control circuit electrically connected to said memory device, said control circuit comprising;

a programmable memory engine, said memory engine generating and outputting requests used to test the memory device,

a memory sequencer electrically connected to said memory engine, said memory sequencer having a first output electrically connected to the memory device, said sequencer using said first output to control the memory device in response to commands received from said memory engine, said memory sequencer having an input for receiving test data from the memory device and a second output for outputting the test data, and

a capture analyzer circuit electrically connected to said memory engine and said second output, said capture analyzer circuit inputting and storing the test data.

14. The test circuit board of claim 13, wherein said control circuit further comprises a host computer interface electrically connected to said memory engine, memory sequencer and said capture analyzer circuit, said host computer interface allowing information and data within said control circuit to be output to a host computer connected to said interface.

15. The test circuit board of claim 14, wherein said host computer interface allows said control circuit to input information and data from the host computer.

16. The test circuit board of claim 14, wherein said host computer interface is a peripheral component interconnect interface.

17. The test circuit board of claim 13, wherein said control circuit further comprises a configuration and control component for configuring and controlling components on said circuit board.

18. The test circuit board of claim 17, further comprising:

a clock; and

delay lines connected to receive clock signals from said clock,

wherein said configuration and control component configures and controls said delay lines to alter a timing of said test circuit board.

19. The test circuit board of claim 17, further comprising a voltage source connected to said control circuit and said memory device, wherein said configuration and control component configures and controls said voltage source.

20. The test circuit board of claim 19, wherein said voltage source is a supply voltage.

21. The test circuit board of claim 19, wherein said voltage source is a reference voltage generator.

22. The test circuit board of claim 13, wherein said control device further comprises internal memory arrays connected to said memory engine, and wherein said memory engine copies the test data within said capture analyzer circuit to said internal memory arrays.

23. The test circuit board of claim 13, wherein said control device further comprises an address buffer electrically connected to said memory engine and said address buffer comprises address test patterns for testing the memory device.

24. The test circuit board of claim 13, wherein said control device further comprises a data buffer electrically connected to said memory engine and said data buffer comprised data test patterns for testing the memory device.

25. The test circuit board of claim 13, wherein said memory engine is a programmable direct memory access controller.

26. The test circuit board of claim 25, wherein said memory engine performs random request spacing.

27. The circuit board of claim 13, wherein said memory device is a double data rate synchronous dynamic random access memory.

28. The test circuit board of claim 13 further comprising a test connector for receiving control information from an external device.

29. The test circuit board of claim 28, wherein said control circuit uses said test connector to output data to the external device.

30. The test circuit board of claim 28, wherein said control circuit uses said test connector to output status information to the external device.

31. The test circuit board of claim 13, wherein said control device is an field programmable gate array device.

32. A test circuit board comprising:

a memory device; and

a programmable control circuit electrically connected to said memory device, said control circuit capable of controlling and testing said memory device and inputting test data from said memory device to evaluate characteristics of said memory device, said control circuit being re-programmable to modify the characteristics of said memory device and the manner in which said control device controls said memory device.

33. A test system comprising:

a computer backplane; and

a test circuit board electrically connected to said backplane, said test circuit board comprising;

a memory device, and

a programmable control circuit electrically connected to said memory device, said control circuit capable of controlling and testing said memory device and inputting test data from said memory device to evaluate characteristics of said memory device, said control circuit outputting the test data to said backplane,

wherein said control circuit is re-programmable to modify the characteristics of said memory device and the manner in which said control device controls said memory device.

34. The test system of claim 33 further comprising a monitor connected to said backplane for displaying the test data.

35. The test system of claim 33 further comprising a printer connected to said backplane for printing the test data.

36. The test system of claim 33 further comprising a storage device connected to said backplane for storing the test data.

37. A test system comprising:

a computer backplane; and

a test circuit board electrically connected to said backplane, said test circuit board comprising a memory device and a programmable control circuit electrically connected to said memory device, said control circuit comprising;

a programmable memory engine, said memory engine generating and outputting requests used to test the memory device,

a memory sequencer electrically connected to said memory engine, said memory sequencer having a first output electrically connected to the memory device, said sequencer using said first output to control the memory device in response to commands received from said memory engine, said memory sequencer having an input for receiving test data from the memory device and a second output for outputting the test data, and

a capture analyzer circuit electrically connected to said memory engine and said second output, said capture analyzer circuit inputting and storing the test data.

38. The test system of claim 37 further comprising a monitor connected to said backplane for displaying the test data.

39. The test system of claim 37 further comprising a printer connected to said backplane for printing the test data.

40. The test system of claim 37 further comprising a storage device connected to said backplane for storing the test data.