METHOD OF USING FILLLER METAL FOR IMPLEMENTING CHANGES IN AN INTEGRATED CIRCUIT DESIGN

• US 20040044983A1
• Filed: 08/30/2002
• Published: 03/04/2004
• Est. Priority Date: 08/30/2002
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Dillon, Michael N., Khakzadi, Khosro, Peterson, Scott A.
• Granted Patent: US 6,748,579 B2
• Time in Patent Office: Days
• US Class Current: 716/21
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A method is provided for fabricating an integrated circuit having a logical function. The method includes fabricating first and second routing layer masks and a first via mask. The first routing layer mask includes power supply segments and signal segments. The second routing layer mask includes signal segments and filler segments, wherein the filler segments are located in unused areas of the second routing layer mask. The first via mask defines vias that electrically couple the filler segments to the power supply segments. If the logical function is changed after the masks have been fabricated, a second via mask is fabricated. The second via mask decouples a filler segment from the power supply segments and couples the filler segment to a signal segment defined by the first routing layer mask to implement the logical function change. The integrated circuit is then fabricated with the first and second routing layer masks and the second via mask.

Claims

1. A method of fabricating photolithography masks for an integrated circuit, the method comprising:

(a) fabricating a set of routing layer masks, which define conductive segments including signal segments, power supply segments and filler segments on various routing layers of the integrated circuit, wherein the filler segments are located in areas unused by the signal segments and the power supply segments;

(b) fabricating a first via mask, which defines electrical connections between the conductive segments on at least two of the routing layers, including connections between the filler segments on one of the layers and the power supply segments on another of the layers;

(c) changing a signal net on the integrated circuit after fabricating at least one of the routing layer masks and the first via mask; and

(d) fabricating a second via mask to replace the first via mask, which decouples a first of the filler segments from a first of the power supply segments and couples the first filler segment into the signal net.

2. The method of claim 1 wherein the signal net is changed in step (c) through step (d) without changing any of the routing layer masks fabricated in step (a).

3. The method of claim 1 wherein the signal net comprises a first signal segment defined on the routing layer on which the first power supply segment is defined and wherein:

step (b) comprises fabricating the first via mask, which defines a first conductive via between the first filler segment and the first power supply segment; and

step (d) comprises fabricating the second via mask to remove the first via and define a second via, which couples the first filler segment to the first signal segment of the signal net.

4. The method of claim 1 wherein:

in step (a), the first power supply segment and a first signal segment are defined by a first of the routing layer masks and the first filler segment and a second signal segment are defined by a second of the routing layer masks;

in step (b), the first via mask defines a first conductive via between the first filler segment and the first power supply segment and a second conductive via between the first and second signal segments, wherein the first and second signal segments and the second via at least partly define the signal net; and

in step (d), the second via mask eliminates the first and second vias and defines a third via, which couples the first filler segment to the first signal segment to define a modified signal net.

5. The method of claim 1 wherein:

step (a) further comprises fabricating a base layer mask set, which defines a first contact of a semiconductor device within the integrated circuit; and

step (d) further comprises fabricating the second via mask define a conductive via between the first filler segment and the first contact.

6. A method of fabricating an integrated circuit having a logical function, the method comprising:

(a) fabricating first and second routing layer masks and a first via mask, wherein the first routing layer mask comprises power supply segments and signal segments, the second routing layer mask comprises signal segments and filler segments, wherein the filler segments are located in unused areas of the second routing layer mask, and the first via mask defines vias that electrically couple the filler segments to the power supply segments;

(b) changing the logical function after step (a);

(c) fabricating a second via mask, which decouples a first of the filler segments from the power supply segments and couples the first filler segment to a first of the signal segments defined by the first routing layer mask to implement the logical function change in step (b); and

(d) fabricating the integrated circuit with the first and second routing layer masks and the second via mask.

7. The method of claim 6 wherein step (d) comprises fabricating the integrated circuit without any changes to the first and second routing layer masks after step (a).

8. The method of claim 6 wherein:

the first via mask defines a first conductive via between the first filler segment and a first of the power supply segments; and

the second via mask removes the first via and defines a second via, which couples the first filler segment to the first signal segment.

9. The method of claim 8 wherein:

the second routing layer mask defines a second signal segment;

the first via mask defines a third conductive via between the first and second signal segments; and

the second via mask removes the first and third vias.

10. The method of claim 6 wherein:

step (a) further comprises fabricating a base layer mask set, which defines a first contact of a semiconductor device within the integrated circuit; and

step (c) further comprises fabricating the second via mask define a conductive via between the first filler segment and the first contact.

11. A collection of masks for fabricating a portion of an integrated circuit, the collection of masks comprising:

a first routing layer mask defining conductive segments, including a plurality of signal segments and at least one power supply segment;

a second routing layer mask defining conductive segments, including a plurality of signal segments and at least one filler segment located in an area unused by the signal segments;

a first via mask, which defines locations of conductive vias between the conductive segments defined by the first and second routing layer masks, including a first via that couples the filler segment to the power supply segment; and

a second via mask which replaces the first via mask, wherein the second via mask eliminates the first via and adds a second via that couples the filler segment to one of the signal segments defined by the first routing layer mask instead of the power supply segment.

12. The collection of masks of claim 11 wherein:

the first routing layer mask defines a first signal segment;

the second routing layer mask defines a second signal segment;

the first via mask defines a third conductive via between the first and second signal segments; and

the second via mask eliminates the first and third vias and adds the second via, which couples the filler segment to the first signal segment.

15. The collection of masks of claim 11 and further comprising:

a base layer mask set, which defines a first contact of a semiconductor device within the integrated circuit; and

the second via mask defines a third conductive via, which couples the first filler segment and the first contact.