Method system and apparatus for multiprocessing

• US 20040045002A1
• Filed: 04/07/2003
• Published: 03/04/2004
• Est. Priority Date: 10/05/2000
• Status: Abandoned Application

• Current Assignee: Wintegra Ltd (Microchip Technology Incorporated)
• Original Assignee: Wintegra Ltd (Microchip Technology Incorporated)
• Inventors: Berger, Ricardo, Yeivin, Yoram
• Application Number:
  US10/398,612
• Publication Number:
  US 20040045002A1
• Time in Patent Office: Days
• US Class Current: 718/102
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues

Abstract

A multi-processing method, system and apparatus having a processor, a request order key issuer connected to the processor which may issue an request order key to a task to be performed by the processor. A resource access order provider may be connected to the processor and may issue access order values to a task in relation to the task'"'"'s request order key.

Claims

1. A method of processing multiple tasks comprising assigning to at least one of the tasks a request order key.

2. The method according to claim 1, further comprising submitting a request order key to a resource access order provider.

3. The method according to claim 2, further comprising accessing a resource in accordance with a resource access value provided by the resource access order provider.

4. The method according to claim 2, further comprising providing a resource access value for each of at least two resource.

5. The method according to claim 4, further comprising accessing more than one resource in accordance with each resource'"'"'s resource access value.

6. The method according to claim 5, wherein one of the resources is a memory register and another of the resources is a computational process.

7. The method according to claim 4, further comprising assigning a resource access value in the same order as a value associated with the submitted request order key.

8. A multi-processing apparatus comprising a processor, a request order key issuer operatively connected to said processor and adapted to issue a request order key to a task to be performed by said processor, and a resource access order provider operatively connected to said processor and adapted to issue a resource access value in accordance with a request order key.

9. The apparatus according to claim 8, further comprising a second processor adapted to submit a task'"'"'s request order key to said resource access order provider.

10. The apparatus according to claim 8, wherein said processor is adapted to run multiple threads.

11. The apparatus according to claim 8, further comprising a resource gatekeeper.

12. The apparatus according to claim 11, wherein said processor may not access a resource for a given task until the task'"'"'s access order value for the resource match'"'"'s a service counter value related to the resource.

13. The apparatus according to claim 12, wherein said resource access order provider is adapted to issue a resource access order value to a task in accordance with the task'"'"'s request order key.

14. The apparatus according to claim 13, wherein said resource access order provider will not issue to a task a resource access order value for a resource until a task with an earlier request ord r key submits its key.

15. A system for multiprocessing comprising:

a multiprocessor having a request order key issuer operatively connected to a processor and adapted to issue an order key to a task to be performed by said processor, and a resource access order provider operatively connected to said processor and adapted to issue a resource access value in accordance with a request order key; and

a serial port operatively connected to said processor.

16. A system according to claim 15, further comprising a data buffer lo operatively connected to said serial port.

17. The system according to claim 15, further comprising a second processor adapted to submit a task'"'"'s request order key to said resource access order provider.

18. The system according to claim 15, wherein said processor is adapted to run multiple threads.

19. The system according to claim 15, further comprising a resource gatekeeper.