Method for forming a low leakage contact in a CMOS imager

• US 20040046104A1
• Filed: 08/11/2003
• Published: 03/11/2004
• Est. Priority Date: 12/08/1998
• Status: Active Grant

• Current Assignee: Howard E. Rhodes
• Original Assignee: Howard E. Rhodes
• Inventors: Rhodes, Howard E.
• Granted Patent: US 6,927,090 B2
• Time in Patent Office: Days
• US Class Current: 250/208.1
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof

Abstract

An imaging device formed as a CMOS semiconductor integrated circuit includes a doped polysilicon contact line between the floating diffusion region and the gate of a source follower output transistor. The doped polysilicon contact line in the CMOS imager decreases leakage from the diffusion region into the substrate which may occur with other techniques for interconnecting the diffusion region with the source follower transistor gate. Additionally, the CMOS imager having a doped polysilicon contact between the floating diffusion region and the source follower transistor gate allows the source follower transistor to be placed closer to the floating diffusion region, thereby allowing a greater photo detection region in the same sized imager circuit.

Claims

1. An imaging device comprising:

a substrate;

a photosensitive area within said substrate for accumulating photogenerated charge in said area;

a floating diffusion region in said substrate for receiving charge from said photosensitive area;

a readout circuit comprising at least an output transistor formed in said substrate;

an insulating layer formed over said substrate; and

,

a doped polysilicon conductor formed in said insulating layer for connecting said floating diffusion region with a gate of said output transistor.

2. The imaging device according to claim 1 wherein the accumulation of charge in said photosensitive area is conducted by a photoconductor.

3. The imaging device according to claim 1, wherein the accumulation of charge in said photosensitive area is controlled by a photogate.

4. The imaging device according to claim 1, wherein said photosensitive area is a photodiode.

5. The imaging device according to claim 1, further comprising a charge transfer region between said photosensitive area and said floating diffusion region, said charge transfer region including a field effect transistor.

6. The imaging device according to claim 1, wherein said doped polysilicon conductor is a composite layered doped polysilicon/refractory metal silicide structure.

7. The imaging device according to claim 1, wherein said doped polysilicon conductor is a composite layered doped polysilicon/refractory metal silicide/insulator structure.

8. The imaging device according to claim 1, wherein said doped polysilicon conductor is a composite layered doped polysilicon/barrier metal silicide/metal structure.

9. The imaging device according to claim 1, including a contact between said doped polysilicon conductor and said floating diffusion region formed by diffusion of dopants from said doped polysilicon conductor into said diffusion region.

10. The imaging device according to claim 1, wherein said substrate includes an n-type implant of arsenic or phosphorous into said substrate at a dopant concentration of about 1.0×

10¹² to about 3.0×

10¹³ ions/cm².

11. The imaging device according to claim 5, wherein the accumulation of charge in said photosensitive area is conducted by a photoconductor.

12. The imaging device according to claim 5, wherein the accumulation of charge in said photosensitive area is conducted by a photogate.

13. The imaging device according to claim 5, wherein said photosensitive area is a photodiode.

14. An imaging device comprising:

a substrate;

a photosensitive area within said substrate for accumulating photogenerated charge in said area;

a floating diffusion region in said substrate for receiving charge from said photosensitive area;

a readout circuit comprising at least an output transistor formed in said substrate;

an insulating layer formed over said substrate;

doped polysilicon plugs formed in said insulating layer which contact said floating diffusion region and said output transistor; and

an interconnector formed over said insulating layer which connects said doped polysilicon plugs.

15. The imaging device according to claim 14, wherein said interconnector is metal.

16. The imaging device according to claim 14, wherein said interconnector is doped polysilicon.

17. The imaging device according to claim 14, wherein the accumulation of charge in said photosensitive area is conducted by a photoconductor.

18. The imaging device according to claim 14, wherein the accumulation of charge in said photosensitive area is controlled by a photogate.

19. The imaging device according to claim 14, wherein said photosensitive area is a photodiode.

20. The imaging device according to claim 14, further comprising a charge transfer region between said photosensitive area and said floating diffusion region, said charge transfer region including a field effect transistor.

21. The imaging device according to claim 14, wherein said doped polysilicon plugs are a composite layered doped polysilicon/barrier metal silicide/metal structure.

22. The imaging device according to claim 14, wherein said substrate includes an n-type implant of arsenic or phosphorous into said substrate at a dopant concentration of about 1.0×

10¹² to about 3.0×

10¹³ ions/cm².

23. The imaging device according to claim 14, including a contact between said polysilicon plug and said floating diffusion region formed by diffusion of dopants from said doped polysilicon plug into said diffusion region.

24. The imaging device according to claim 20, wherein the accumulation of charge in said photosensitive area is conducted by a photoconductor.

25. The imaging device according to claim 20, wherein the accumulation of charge in said photosensitive area is conducted by a photogate.

26. The imaging device according to claim 20, wherein said photosensitive area is a photodiode.

27. The imaging device according to claim 15, wherein said metal interconnector includes tungsten.

28. The imaging device according to claim 15, wherein said metal interconnector includes at least one of Ti, Al, W, Cu, nitrides thereof, mixtures thereof and alloys thereof.

29. The imaging device according to claim 16, wherein said doped polysilicon conductor is a composite layered doped polysilicon/refractory metal silicide structure.

30. The imaging device according to claim 29, wherein said doped polysilicon conductor is a composite layered doped polysilicon/refractory metal silicide/insulator structure.

31. An imaging device comprising

a semiconductor integrated circuit substrate;

a photosensitive device formed on said substrate for accumulating photogenerated charge in an underlying region of said substrate;

a floating diffusion region in said substrate for receiving said photogenerated charge;

a readout circuit comprising at least an output transistor formed in said substrate;

an insulating layer formed over said substrate; and

said floating diffusion region being connected to said output transistor by a doped polysilicon contact formed at least partially within said insulating layer.

32. The imaging device according to claim 31, wherein said photosensitive device is a photogate.

33. The imaging device according to claim 31, wherein said photosensitive device is a photodiode.

34. The imaging device according to claim 31, wherein said photosensitive device is a photoconductor.

35. The imaging device according to claim 31, wherein a contact between said buried conductor and said floating diffusion region is formed by diffusion of dopants from said doped polysilicon contact into said diffusion region.

36. The imaging device according to claim 31, wherein said doped polysilicon contact is a composite layered doped polysilicon/barrier metal silicide/metal structure.

37. The imaging device according to claim 31, wherein said substrate includes an n-type implant of arsenic or phosphorous into said substrate at a dopant concentration of about 1.0×

10¹² to about 3.0×

10¹³ ions/cm².

38. The imaging device according to claim 31, further comprising at least one charge transfer device for transferring charge from said photosensitive area to said floating diffusion region in accordance with a control signal applied to a control terminal.

39. The imaging device according to claim 31, wherein said doped polysilicon conductor is a composite layered doped polysilicon/refractory metal silicide structure.

40. The imaging device according to claim 39, wherein said doped polysilicon conductor is a composite layered doped polysilicon/refractory metal silicide/insulator structure.

41. The imaging device according to claim 31, wherein said output transistor is formed adjacent to said floating diffusion region on said substrate.

42. The imaging device according to claim 31, further comprising a reset transistor for resetting said floating diffusion region to a predetermined voltage.

43. The imaging device according to claim 31, wherein said floating diffusion region is an n-doped region in a p-well.

44. The imaging device according to claim 32, wherein said photogate is formed of doped polysilicon.

45. The imaging device according to claim 33, further comprising a lightly doped n region beneath said photodiode.

46. An imaging device comprising

a semiconductor integrated circuit substrate;

a photosensitive device formed on said substrate for accumulating photogenerated charge in an underlying region of said substrate;

a floating diffusion region in said substrate for receiving said photogenerated charge;

a readout circuit comprising at least an output transistor formed in said substrate;

an insulating layer formed over said substrate; and

doped polysilicon plugs formed in said insulating layer which contact said floating diffusion region and said output transistor; and

an interconnector formed over said insulating layer which connects said doped polysilicon plugs.

47. The imaging device according to claim 46, wherein said interconnector is a metal.

48. The imaging device according to claim 46, wherein said interconnector is doped polysilicon.

49. The imaging device according to claim 46, wherein said photosensitive device is a photogate.

50. The imaging device according to claim 46, wherein said photosensitive device is a photodiode.

51. The imaging device according to claim 46, wherein said photosensitive device is a photoconductor.

52. The imaging device according to claim 46, including a contact between said doped polysilicon plug and said floating diffusion region formed by diffusion of dopants from said doped polysilicon plug into said diffusion region.

53. The imaging device according to claim 46, further comprising at least one charge transfer device for transferring charge from said photosensitive area to said floating diffusion region in accordance with a control signal applied to a control terminal.

54. The imaging device according to claim 46, wherein said doped polysilicon plugs are a composite layered doped polysilicon/barrier metal silicide/metal structure.

55. The imaging device according to claim 46, wherein said substrate includes an n-type implant of arsenic or phosphorous into said substrate at a dopant concentration of about 1.0×

10¹² to about 3.0×

10¹³ ions/cm².

56. The imaging device according to claim 46, wherein said output transistor is formed adjacent to said floating diffusion region on said substrate.

57. The imaging device according to claim 46, further comprising a reset transistor for resetting said floating diffusion region to a predetermined voltage.

58. The imaging device according to claim 46, wherein said floating diffusion region is an n-doped region in a p-well.

59. The imaging device according to claim 49, wherein said photogate is formed of doped polysilicon.

60. The imaging device according to claim 50, further comprising a lightly doped n region beneath said photodiode.

61. The imaging device according to claim 47, wherein said metal interconnector includes tungsten.

62. The imaging device according to claim 47, wherein said metal interconnector includes at least one of Ti, Al, W, Cu, nitrides thereof, mixtures thereof and alloys thereof.

63. The imaging device according to claim 48, wherein said doped polysilicon conductor is a composite layered doped polysilicon/refractory metal silicide structure.

64. The imaging device according to claim 63, wherein said doped polysilicon conductor is a composite layered doped polysilicon/refractory metal silicide/insulator structure.

65. A method for generating output signals corresponding to an image focused on a sensor array having rows and columns of pixel sensors, the method comprising the steps of:

sequentially activating each row of sensors of said array for a period of time;

detecting a first voltage at a node of an activated sensor, which corresponds to collected charges produced by a detected image;

resetting the voltage of said node to a first predetermined voltage by a reset transistor;

transferring image generated electrical charges collected by said activated sensor to said node, the voltage at the node changing from a first reset voltage to a second voltage corresponding to the respective amount of transferred electrical charges;

detecting the second voltage at the node of said activated sensor; and

generating an output signal by transferring charge from said node of said activated sensor to an output transistor via a doped polysilicon contact formed on an insulating layer.

66. The method for generating an output signal according to claim 65, wherein said activated sensor is a photogate.

67. The method for generating an output signal according to claim 65, wherein said activated sensor is a photodiode.

68. The method for generating an output signal according to claim 65, wherein said activated sensor is a photoconductor.

69. The method for generating an output signal according to claim 65, wherein said transferring of electrical charges collected by said activated sensor to said diffusion well is performed by a field effect transistor.

70. The method for generating an output signal according to claim 65, wherein said diffusion node is a floating diffusion node.

71. The method for generating an output signal according to claim 65, wherein a contact between said buried conductor and said node is formed by diffusion of dopants from said doped polysilicon contact into said diffusion region.

72. The method for generating an output signal according to claim 65, wherein said doped polysilicon conyact is a composite layered doped polysilicon/barrier metal silicide/metal structure.

73. The method for generating an output signal according to claim 65, wherein said substrate includes an n-type implant of arsenic or phosphorous into said substrate at a dopant concentration of about 1.0×

10¹² to about 3.0×

10³ ions/cm².

74. The method for generating an output signal according to claim 65, wherein said doped polysilicon conductor is a composite layered doped polysilicon/refractory metal silicide structure.

75. The method for generating an output signal according to claim 74, wherein said doped polysilicon conductor is a composite layered doped polysilicon/refractory metal silicide/insulator structure.

76. An imaging system for generating output signals based on an image focused on the imaging system, the imaging system comprising:

a plurality of pixel cells arranged into an array of rows and columns, each pixel cell being operable to generate a voltage at a diffusion node corresponding to detected light intensity by the cell;

a row decoder having a plurality of control lines connected to the cell array, each control line being connected to the cells in a respective row, wherein the row decoder is operable to activate the cells in a row; and

a plurality of output circuits each including a respective output transistor, each output circuit being connected to a respective cell of said array, each circuit being operable to store voltage signals received from a respective cell and to provide a cell output signal; and

a plurality of doped polysilicon contacts for respectively interconnecting a diffusion node of a pixel cell with a gate of a source follower transistor.

77. The imaging system according to claim 76, wherein said output transistor is a source follower transistor and the diffusion node is connected to said source follower transistor by a buried contact connection formed over an insulating layer formed over the substrate of said pixel cell.

78. The imaging system according to claim 76, wherein said active pixel cells include a photogate.

79. The imaging system according to claim 76, wherein said active pixel cells include a photodiode.

80. The imaging system according to claim 76, wherein said active pixel cells include a photoconductor.

81. The imaging system according to claim 77, wherein said source follower transistor is formed adjacent to said diffusion node.

82. The imaging system according to claim 76, further comprising at least one charge transfer device for transferring charge from a photosensitive area to a floating diffusion region in said pixel cell in accordance with a control signal applied to a control terminal.

83. The imaging system according to claim 76, wherein said doped polysilicon contacts are a composite layered doped polysilicon/barrier metal silicide/metal structure.

84. The imaging system according to claim 76, wherein said substrate includes an n-type implant of arsenic or phosphorous into said substrate at a dopant concentration of about 1.0×

10¹² to about 3.0×

10¹³ ions/cm².

85. The imaging system according to claim 76, wherein said doped polysilicon conductor is a composite layered doped polysilicon/refractory metal silicide structure.

86. The imaging system according to claim 76, including a contact between said doped polysilicon contact and said floating diffusion region formed by diffusion of dopants from said doped polysilicon contact into said diffusion region.

87. The imaging system according to claim 82, wherein the accumulation of charge in said photosensitive area is conducted by a photoconductor.

88. The imaging system according to claim 82, wherein the accumulation of charge in said photosensitive area is conducted by a photogate.

89. The imaging system according to claim 82, wherein said photosensitive area is a photodiode.

90. A processing system comprising:

(i) a processor; and

(ii) a CMOS imaging device coupled to said processor and including;

a substrate;

a photosensitive area within said substrate for accumulating photogenerated charge in said area;

a floating diffusion region in said substrate for receiving charge from said photosensitive area;

a readout circuit comprising at least an output transistor formed in said substrate;

an insulating layer formed over said substrate; and

a doped polysilicon conductor formed at least partially within said insulating layer for interconnecting said floating diffusion region with said output transistor.

91. The system according to claim 90, further comprising at least one charge transfer device for transferring charge from said photosensitive area to said floating diffusion region in accordance with a control signal applied to a control terminal.

92. The system according to claim 90, wherein the accumulation of charge in said photosensitive area is conducted by a photogate.

93. The system according to claim 90, wherein said photosensitive area is a photodiode.

94. The system according to claim 90, wherein said photosensitive area is a photoconductor.

95. The system according to claim 90, including a contact between said buried conductor and said floating diffusion region formed by diffusion of dopants from said doped polysilicon conductor into said diffusion region.

96. The system according to claim 90, wherein said doped polysilicon conductor is a composite layered doped polysilicon/barrier metal silicide/metal structure.

97. The system according to claim 90, wherein said substrate includes an n-type implant of arsenic or phosphorous into said substrate at a dopant concentration of about 1.0×

10¹² to about 3.0×

10¹³ ions/cm².

98. The system according to claim 90, wherein said doped polysilicon conductor is a composite layered doped polysilicon/refractory metal silicide structure.

99. The system according to claim 98, wherein said doped polysilicon conductor is a composite layered doped polysilicon/refractory metal silicide/insulator structure.

100. The system according to claim 91, wherein the accumulation of charge in said photosensitive area is controlled by a photoconductor.

101. The system according to claim 91, wherein the accumulation of charge in said photosensitive area is controlled by a photogate.

102. The system according to claim 91, wherein said photosensitive area is a photodiode.

103. A processing system comprising:

(i) a processor; and

(ii) a CMOS imaging device coupled to said processor and including;

a substrate;

a photosensitive area within said substrate for accumulating photogenerated charge in said area;

a floating diffusion region in said substrate for receiving charge from said photosensitive area;

a readout circuit comprising at least an output transistor formed in said substrate;

an insulating layer formed over said substrate;

doped polysilicon plugs formed in said insulating layer which contact said floating diffusion region and said output transistor; and

an interconnector formed over said insulating layer which connects said doped polysilicon plugs.

104. The system according to claim 103, wherein said interconnector is a metal.

105. The system according to claim 103, wherein said interconnector is doped polysilicon.

106. The system according to claim 103, further comprising at least one charge transfer device for transferring charge from said photosensitive area to said floating diffusion region in accordance with a control signal applied to a control terminal.

107. The system according to claim 103, wherein the accumulation of charge in said photosensitive area is conducted by a photogate.

108. The system according to claim 103, wherein said photosensitive area is a photodiode.

109. The system according to claim 103, wherein said photosensitive are is a photoconductor.

110. The system according to claim 103, including a contact between said doped polysilicon plug and said floating diffusion region formed by diffusion of dopants from said doped polysilicon plug into said diffusion region.

111. The system according to claim 103, wherein said interconnector is a composite layered doped polysilicon/barrier metal silicide/metal structure.

112. The system according to claim 103, wherein said substrate includes an n-type implant of arsenic or phosphorous into said substrate at a dopant concentration of about 1.0×

10¹² to about 3.0×

10¹³ ions/cm².

113. The system according to claim 106, wherein the accumulation of charge in said photosensitive area is controlled by a photoconductor.

114. The system according to claim 106, wherein the accumulation of charge in said photosensitive area is controlled by a photogate.

115. The system according to claim 106, wherein said photosensitive area is a photodiode.

116. The system according to claim 105, wherein said doped polysilicon conductor is a composite layered doped polysilicon/refractory metal silicide structure.

117. The system according to claim 116, wherein said doped polysilicon conductor is a composite layered doped polysilicon/refractory metal silicide/insulator structure.

118. The system according to claim 104, wherein said metal interconnector includes tungsten.

119. The system according to claim 104, wherein said metal interconnector includes at least one of Ti, Al, W, Cu, nitrides thereof, mixtures thereof and alloys thereof.

120. A method of forming a contact line between a diffusion node and an output transistor in a CMOS imager, comprising the steps of:

providing a substrate having a first conductivity;

forming a diffusion region having a second conductivity in said substrate which functions as said diffusion node;

forming an insulating layer on said substrate;

forming an output transistor on said substrate;

selectively removing at least a portion of said insulating layer over said diffusion region;

selectively removing at least a portion of said insulating layer over the gate of said output transistor; and

forming a continuously conductive layer of doped polysilicon directly over at least a portion of said insulating layer to connect said diffusion contact and said output transistor gate.

121. The method according to claim 120, wherein said insulating layer is silicon dioxide.

122. The method according to claim 120, wherein a contact between said doped polysilicon conductor and said floating diffusion region is formed by diffusion of dopants from said doped polysilicon conductor into said diffusion region.

123. The method according to claim 120, further comprising forming a composite layered doped polysilicon/barrier metal silicide/metal structure to connect said diffusion contact with said output transistor gate.

124. The method according to claim 120, wherein said substrate of a first conductivity includes an n-type implant of arsenic or phosphorous into said substrate at a dopant concentration of about 1.0×

10¹² to about 3.0×

10¹³ ions/cm².

125. The method according to claim 120, further comprising forming a refractory metal silicide layer around the periphery of said polysilicon conductive layer.

126. The method according to claim 125, further comprising an insulating layer around the periphery of said refractory metal silicide layer.

127. The method according to claim 120, wherein said first conductivity type is p-type and said second conductivity type is n-type.

128. The method according to claim 120, wherein said output transistor is a source follower transistor formed adjacent to said diffusion region.

129. The method according to claim 120, wherein said insulating layer is removed by etching.

130. A method of forming a buried contact line between a diffusion node and an output transistor in a CMOS imager, comprising the steps of:

providing a substrate having a first conductivity;

forming a diffusion region having a second conductivity in said substrate which functions as said diffusion node;

forming an insulating layer on said substrate;

forming an output transistor on said substrate;

selectively removing at least a portion of said insulating layer to form a first trench over said diffusion region;

selectively removing at least a portion of said insulating layer to forma second trench over the gate of said output transistor;

forming first and second conductive doped polysilicon plugs in said first and second trenches respectively; and

forming a metal interconnector over said insulating layer to connect said diffusion contact and said output transistor gate by connecting said first and second doped polysilicon plugs.

131. The method according to claim 130, wherein said insulating layer is silicon dioxide.

132. The method according to claim 130, wherein a contact between said first doped polysilicon plug and said floating diffusion region is formed by diffusion of dopants from said first doped polysilicon plug into said diffusion region.

133. The method according to claim 130, wherein said substrate of a first conductivity includes an n-type implant of arsenic or phosphorous into said substrate at a dopant concentration of about 1.0×

10¹² to about 3.0×

10¹³ ions/cm².

134. The method according to claim 130, wherein said first conductivity type is p-type and said second conductivity type is n-type.

135. The method according to claim 130, wherein said output transistor is a source follower transistor formed adjacent to said diffusion region.

136. The method according to claim 130, wherein said insulating layer is removed by etching.

137. The method according to claim 130, wherein said metal interconnector is formed of at least a tungsten metal.

138. The method according to claim 130, wherein said metal interconnector includes at least one of Ti, Al, W, Cu, nitrides thereof, mixtures thereof and alloys thereof.

139. The method according to claim 137, wherein said metal is deposited by sputtering.

140. The method according to claim 138, wherein said metal is deposited by sputtering.

141. A method of forming a contact line between a floating diffusion node and a source follower transistor in a CMOS imager, comprising the steps of:

providing a semiconductor substrate doped to a first conductivity;

forming a floating diffusion region of a second conductivity in said substrate;

forming an insulating layer of silicon dioxide over at least a portion of said substrate;

forming a source follower transistor adjacent to said floating diffusion region;

selectively removing at least a portion of said insulating layer over the gate of said output transistor;

selectively etching at least a portion of said insulating layer to over said diffusion region and said source follower transistor gate;

forming a doped polysilicon layer on at least a portion of said insulating layer to connect said floating diffusion contact and said source follower transistor gate.

142. The method according to claim 141, wherein a contact between said doped polysilicon layer and said floating diffusion region is formed by diffusion of dopants from said doped polysilicon conductor into said floating diffusion region.

143. The method according to claim 141, wherein said substrate includes an n-type implant of arsenic or phosphorous into said substrate at a dopant concentration of about 1.0×

10¹² to about 3.0×

10¹³ ions/cm².

144. A method of forming a buried contact line between a diffusion node and an output transistor in a CMOS imager, comprising the steps of:

providing a substrate having a first conductivity;

forming a diffusion region having a second conductivity in said substrate which functions as said diffusion node;

forming an insulating layer of silicon dioxide over at least a portion of said substrate, wherein said insulating layer is formed over at least said floating diffusion region;

forming an output transistor area over said substrate;

selectively removing at least a portion of said insulating layer to form a diffusion contact area over said diffusion region; and

forming a continuously conductive layer of doped polysilicon directly in said insulating layer to connect said diffusion contact and said output transistor.

145. The method according to claim 144, wherein said insulating layer is silicon dioxide.

146. The method according to claim 144, further comprising forming a refractory metal silicide layer over a periphery of said polysilicon conductive layer.

147. The method according to claim 144, wherein said first conductivity type is p-type and said second conductivity type is n-type.

148. The method according to claim 144, wherein said output transistor is a source follower transistor formed adjacent to said diffusion region.

149. The method according to claim 144, wherein said insulating layer is removed by etching.