Semiconductor device and method for manufacturing the same

• US 20040046226A1
• Filed: 09/08/2003
• Published: 03/11/2004
• Est. Priority Date: 09/09/2002
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Nakano, Takashi, Mizuno, Shoji, Himi, Hiroaki
• Granted Patent: US 7,132,347 B2
• Time in Patent Office: Days
• US Class Current: 257/499
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/7317 Bipolar thin film transistors
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors

Abstract

A semiconductor device includes a common diffusion structure formed in each region of a substrate in which semiconductor components are formed. The diffusion structures are separated into sections by trenches to form semiconductor components. The trenches define sizes of the semiconductor components and isolate the semiconductor components from the surrounding area.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a diffusion structure formed on the semiconductor substrate;

a trench formed in the diffusion structure; and

a semiconductor component separated and isolated from surrounding areas thereof in the substrate by the trench, wherein the trench defines a size of the semiconductor component.

2. The semiconductor device according to claim 1, further comprising:

a plurality of trenches formed in the diffusion structure; and

a plurality of semiconductor components of a kind separated and isolated from surrounding areas thereof in the substrate by the trenches, wherein the trenches define sizes of the semiconductor components.

3. The semiconductor device according to claim 1, wherein the semiconductor substrate is a silicon on insulator substrate.

4. The semiconductor device according to claim 3, wherein:

the silicon on insulator substrate includes an insulating layer and a semiconductor layer;

the semiconductor layer is formed on the insulating layer; and

the semiconductor layer has a thickness equal to or less than five micrometers.

5. The semiconductor device according to claim 1, wherein the trench is filled in with borophosphosilicate glass.

6. The semiconductor device according to claim 1, wherein the diffusion structure includes a repeated pattern.

7. The semiconductor device according to claim 1, wherein the diffusion structure includes diffusion regions in rectangular shape arranged in a repeated pattern.

8. The semiconductor device according to claim 1, wherein the semiconductor component is an analog component for processing an analog signal.

9. The semiconductor device according to claim 8, wherein the analog component is a bipolar transistor.

10. The semiconductor device according to claim 1, wherein the semiconductor device is a power component for controlling power supply.

11. The semiconductor device according to claim 10, wherein the power component is a laterally diffused metal oxide semiconductor transistor.

12. The semiconductor device according to claim 10, wherein the power component is an insulated gate bipolar transistor.

13. The semiconductor device according to claim 1, wherein the semiconductor device is a hybrid-IC in which different kinds of semiconductors are integrated in a single chip.

14. A method for manufacturing a semiconductor device that includes a semiconductor component formed on a substrate, comprising:

forming a diffusion structure larger than the semiconductor component in a region of the substrate in which the semiconductor component is formed;

separating a part of the diffusion structure from a surrounding area thereof by the trench to form the semiconductor component along with defining a size of the semiconductor component; and

connecting a metallization pattern to the semiconductor component.

15. The method according to claim 14, wherein the semiconductor substrate, in a region of which the diffusion structure is formed, is a silicon on insulator substrate.

16. The method according to claim 15, wherein:

the silicon on insulator substrate includes a semiconductor layer formed on an insulating layer; and

the semiconductor layer is equal to or less than five micrometers.

17. The method according to claim 14 further comprising filling in the trench with borophosphosilicate glass.

18. The method according to claim 14, wherein the diffusion structure is formed including a repeated pattern in the region.

19. The method according to claim 14, wherein the diffusion structure is formed including diffusion regions shaped in a rectangular.

20. The method according to claim 14, wherein the semiconductor device formed in separating step is an analog component for processing an analog signal.

21. The method according to claim 20, wherein the analog component is a bipolar transistor.

22. The method according to claim 14, wherein the semiconductor device formed in separating step is a power component for controlling power supply.

23. The method according to claim 22, wherein the power component is an insulated gate bipolar transistor.

24. The method according to claim 22, wherein the power component is a laterally diffused metal oxide semiconductor transistor.

25. The method according to claim 14, wherein the semiconductor device manufactured by the method is a hybrid IC including different kinds of semiconductor components integrated into a single chip.

26. A method for manufacturing a semiconductor device that includes a plurality of semiconductor components of a kind in a region of a semiconductor substrate, comprising:

forming a common diffusion structure in the region in which the semiconductor components are formed;

separating parts of the diffusion structure from a surrounding area thereof by trenches to form the semiconductor components along with defining sizes of the semiconductor components; and

connecting metallization patterns to the semiconductor components.

27. The method according to claim 26, wherein the semiconductor substrate, in a region of which the diffusion structure is formed, is a silicon on insulator substrate.

28. The method according to claim 27, wherein:

the silicon on insulator substrate includes a semiconductor layer formed on an insulating layer; and

the semiconductor layer is equal to or less than five micrometers.

29. The method according to claim 26, further comprising filling in the trench with borophosphosilicate glass.

30. The method according to claim 26, wherein the diffusion structure is formed including a repeated pattern in the region.

31. The method according to claim 26, wherein the diffusion structure is formed including diffusion regions shaped in a rectangular.

32. The method according to claim 26, wherein the semiconductor device formed in separating step is an analog component for processing an analog signal.

33. The method according to claim 32, wherein the analog component is a bipolar transistor.

34. The method according to claim 26, wherein the semiconductor device formed in separating step is a power component for controlling power supply.

35. The method according to claim 34, wherein the power component is an insulated gate bipolar transistor.

36. The method according to claim 34, wherein the power component is a laterally diffused metal oxide semiconductor transistor.

37. The method according to claim 26, wherein the semiconductor device manufactured by the method is a hybrid IC including different kinds of semiconductor components integrated into a single chip.