Redundant clock source
First Claim
1. A clock system comprising:
- first and second oscillators having the same frequency;
means for coupling a first waveform derived from said first oscillator and a second waveform derived from said second oscillator to produce a third waveform;
a resonant filter connected to receive said third waveform and generate clock edges; and
an output buffer connected to receive said clock edges and generate a master clock signal.
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Accused Products
Abstract
A redundant clock source provides a stable clock source for digital system. The clock source uses two oscillators to generate a clock signal. If one of the oscillators fails, the clock signal is generated from the other oscillator until the failed oscillator is replaced. Special filtering of the waveforms produced by the oscillators makes the clock source is resistant to jitter from the oscillators and transients that occur when an oscillator fails. This allows the clock source to not only use a redundant oscillator in an attempt to eliminate a single point of failure, but to also provide a stable clock signal even if one oscillator fails.
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Citations
12 Claims
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1. A clock system comprising:
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first and second oscillators having the same frequency;
means for coupling a first waveform derived from said first oscillator and a second waveform derived from said second oscillator to produce a third waveform;
a resonant filter connected to receive said third waveform and generate clock edges; and
an output buffer connected to receive said clock edges and generate a master clock signal. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method of producing a clock signal in a redundant clock system compring the steps of:
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deriving first and second waveforms from a first and second oscillators, said oscillators having a same frequency;
coupling said first and second waveforms to produce a third waveform; and
filtering said third waveform with a resonant filter to produce clock edges; and
passing said clock edges to an output buffer, said output buffer generating a master clock signal. - View Dependent Claims (8, 9, 10, 11, 12)
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Specification