Methods of forming vertical power devices having deep and shallow trenches therein

• US 20040048488A1
• Filed: 09/08/2003
• Published: 03/11/2004
• Est. Priority Date: 11/16/2000
• Status: Abandoned Application

• Current Assignee: Bantval Jayant Baliga
• Original Assignee: Bantval Jayant Baliga
• Inventors: Baliga, Bantval Jayant
• Application Number:
  US10/657,586
• Publication Number:
  US 20040048488A1
• Time in Patent Office: Days
• US Class Current: 438/719
• CPC Class Codes: H01L 2223/6627 Waveguides, e.g. microstrip line, strip line, coplanar line
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/371 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/40095 Kinked
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/73255 Bump and strap connectors
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/83801 Soldering or alloying
• CPC Class Codes: H01L 2224/84 using a strap connector
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/37 of an individual strap connector
• CPC Class Codes: H01L 24/40 of an individual strap connector
• CPC Class Codes: H01L 24/41 of a plurality of strap connectors
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 27/088 : the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0696 : of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/402 : Field plates
• CPC Class Codes: H01L 29/407 : Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 : for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/66712 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7803 : structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13063 : Metal-Semiconductor Field-Effect Transistor [MESFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/1903 : including wave guides
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

Methods of forming vertical power devices include the steps of forming first and second deep trenches in a semiconductor substrate having a drift region of first conductivity type therein that extends into a mesa defined between first and second opposing sidewalls of the first and second deep trenches, respectively. Steps are also performed to form a UMOSFET in the mesa and form first and second base shielding regions of second conductivity type that extend into the mesa and are self-aligned with the first and second opposing sidewalls.

Claims

1. A method of forming a vertical power device, comprising the steps of:

forming first and second deep trenches in a semiconductor substrate having a drift region of first conductivity type therein that extends into a mesa defined between first and second opposing sidewalls of the first and second deep trenches, respectively; and

forming a UMOSFET in the mesa.

2. The method of claim 1, further comprising the step of forming first and second base shielding regions of second conductivity type that extend into the mesa and are self-aligned with the first and second opposing sidewalls.

3. The method of claim 2, further comprising the step of forming a transition region of first conductivity type that extends between the drift region and a base region of second conductivity type within the UMOSFET.

4. A method of forming a vertical MOSFET, comprising the steps of:

implanting base region dopants of second conductivity type into an active portion of a semiconductor substrate having a drift region of first conductivity type therein;

forming a first mask having openings therein on the active portion of the semiconductor substrate;

implanting shielding region dopants of second conductivity type into the active portion of the substrate, using the first mask as an implant mask;

driving-in the implanted base and shielding region dopants to define a base region and a plurality of base shielding regions that extend laterally underneath the first mask and vertically through the base region and into the drift region;

etching first and second deep trenches into the semiconductor substrate to define a drift region mesa therebetween, using the first mask as an etching mask;

forming first and second insulated source electrodes in the first and second trenches, respectively;

implanting source region dopants of first conductivity type into the drift region mesa;

driving-in the implanted source region dopants to define a source region in the base region;

forming a shallow trench that extends in the drift region mesa and has a sidewall extending adjacent the base and source regions;

forming an insulated gate electrode in the shallow trench; and

forming a source electrode that electrically connects the first and second insulated source electrodes, the source region and the base region together.

5. A method of forming a vertical power device, comprising the steps of:

forming first and second stripe-shaped trenches that extend in parallel and in a first direction across a semiconductor substrate having a drift region therein that extends adjacent a face thereof;

forming first and second insulated electrodes in the first and second stripe-shaped trenches, respectively;

forming first and second base regions of second conductivity type that each extend from a sidewall of said first stripe-shaped trench to an opposing sidewall of said second stripe-shaped trench and define a respective P-N junction with the drift region;

forming first and second source regions of first conductivity type in said first and second base regions, respectively;

forming a source electrode that extends on the first face and is electrically connected to said first and second insulated electrodes and to said first and second source regions; and

forming an insulated gate electrode that extends in a second direction across the first face of said semiconductor substrate that is orthogonal to the first direction.

6. The method of claim 5, wherein said step of forming an insulated gate electrode comprises forming an insulated gate electrode that extends opposite the first and second base regions and the drift region and is positioned so that during forward on-state conduction in the vertical power device, majority carriers provided by the first and second source regions flow across the first and second base regions in a direction parallel to the first and second stripe-shaped trenches.