Feedback random number generation method and system

• US 20040049525A1
• Filed: 09/06/2002
• Published: 03/11/2004
• Est. Priority Date: 09/06/2002
• Status: Abandoned Application

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Koninklijke Philips Electronics N.V. (Koninklijke Philips N.V.)
• Inventors: Hars, Laszlo
• Application Number:
  US10/236,178
• Publication Number:
  US 20040049525A1
• Time in Patent Office: Days
• US Class Current: 708/250
• CPC Class Codes: G06F 2207/583 Serial finite field implementation, i.e. serial implementation of finite field arithmetic, generating one new bit or trit per step, e.g. using an LFSR or several independent LFSRs; also includes PRNGs with parallel operation between LFSR and outputs
• CPC Class Codes: G06F 7/584 using finite field arithmetic, e.g. using a linear feedback shift register
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: H03K 3/84 Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators

Abstract

A physical random number generator operates to generate a true random bit sequence while a linear feedback shift register and a clock collectively operate to provide a plurality of feedback random bit sequences. In operation, the linear feedback shift register periodically latches the feedback random bit sequences in response to a clock signal having a predetermined operating frequency from the clock. In latching the feedback random bit sequences, the linear feedback shift register includes a plurality of bi-stable latches for linearly shifting a mixed random bit sequence outputted by an XOR gate, which is combined with the true random bit sequence. A decimator receives a feedback random bit sequence and provides an output random bit sequence that is representative of a selective outputting of the feedback random bit sequence.

Claims

1. A random number generator system, comprising:

a physical random number generator operable to generate one or more true random bit sequences;

a linear feedback shift register operable to periodically latch one or more feedback random bit sequences as a function of the one or more true random bit sequences; and

a clock operable to provide a clock signal having a predetermined operating frequency for triggering a periodic latching of the one or more feedback random bit sequences by said linear feedback shift register.

2. The random number generation system, further comprising:

a decimator operable to provide one or more output random bit sequences that are representative of a selective outputting of the one or more feedback random bit sequences.

3. A random number generator system, comprising:

a physical random number generator operable to generate a true random bit sequence;

a linear feedback shift register operable to periodically latch one or more feedback random bit sequences as a function of the true random bit sequence; and

a clock operable to provide a clock signal having a predetermined operating frequency for triggering a periodic latching of the one or more feedback random bit sequences (FRB₁-FRB_Z) by said linear feedback shift register.

4. The random number generator system of claim 3, comprising:

a decimator operable to provide an output random bit sequences that is representative of a selective outputting of a first feedback random bit sequence of the one or more feedback random bit sequences.

5. The random number generation system of claim 3, wherein said linear feedback shift register includes

a logic circuit operable to generate one or more mixed random bit sequences in response to a reception of the true random bit sequence and a reception of a first feedback random bit sequence of the one or more feedback random bit sequences, and

at least one bi-stable latch operable to generate the one or more feedback random bit sequences in response to a reception of the one or more mixed random bit sequences and the clock signal.

6. A random number generator system, comprising:

a physical random number generator operable to provide one or more true random bit sequences;

a plurality of linear feedback shift registers operable to receive the one or more true random bit sequences, wherein a first linear feedback shift register is operable to periodically latch one or more feedback random bit sequences as a function of the one or more true random bit sequences; and

a clock operable to provide a clock signal having a predetermined operating frequency for triggering a periodic latching of the one or more feedback random bit sequences by said first linear feedback shift register.

7. The random number generation system of claim 6, further comprising:

a plurality of decimators operable to output one or more output random bit sequences that are representative of a selective outputting of the feedback random bit sequences.

8. The random number generation system of claim 7, further comprising:

a logic circuit operable to provide a system random bit sequence as a function of the one or more output random bit sequences.

9. The random number generation system of claim 6, further comprising:

a logic circuit operable to provide a system random bit sequence as a function of the feedback random bit sequences.

10. The random number generation system of claim 6, wherein said first linear feedback shift register includes

a logic circuit operable to generate one or more mixed random bit sequences in response to a reception of a first true random bit sequence and a reception of a first feedback random bit sequence of the one or more feedback random bit sequences;

and

at least one bi-stable latch operable to generate the one or more feedback random bit sequences in response to a reception of the one or more mixed random bit sequences and the clock signal.