Terminal apparatus

• US 20040049606A1
• Filed: 08/13/2003
• Published: 03/11/2004
• Est. Priority Date: 10/09/1995
• Status: Active Grant

• Current Assignee: SOTA Semiconductor LLC (Acacia Research Corporation)
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Nakagawa, Tetsuya, Noguchi, Koki, Baji, Toru, Hatano, Yuji, Sagesaka, Yasuhiro
• Granted Patent: US 6,993,597 B2
• Time in Patent Office: Days
• US Class Current: 710/1
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 15/7807 System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.

Claims

1. A terminal apparatus comprising a micro-processor having a DSP function (600) and a CPU function integrated with each other as a single bus master, and an internal memory space and an external memory space integrated as a single memory space, wherein

the DSP function includes a plurality of internal memories (602, 603) and a plurality of buses (604, 605) for connecting said internal memories for executing the non-recursive filter operation constituting a basic operation of the digital signal processing at the rate of one cycle per tap,

and said CPU function (600) is capable of executing a basic instruction for any of such operations as calculation, internal memory access and data transfer at the rate of an instruction per cycle, and thereby capable of compiling a program written in a high-level language into said basic instruction and executing said basic instruction efficiently.

2. A terminal apparatus according to claim 1, further comprising an integrated peripheral circuit (503) accessible from both the DSP function (600) and the CPU function (600).

3. A terminal apparatus according to claim 1, wherein said microprocessor comprises a directly-coupled interface (1006) for an external memory having high-speed access mode.

4. A terminal apparatus according to claim 1, wherein said internal memory has built therein an audio coding/decoding program and a communication path coding/decoding program (801), and said external memory has stored therein a communication protocol program and a user interface program (803).

5. A terminal apparatus according to claim 1, wherein said microprocessor comprises a cache memory (704) and means for controlling the cache memory.

6. A terminal apparatus according to claim 2, wherein said microprocessor (1300) is capable of transferring a plurality of input-output samples collectively from a serial input-output circuit to the internal memory and the external memory.

7. A terminal apparatus according to claim 1, wherein said microprocessor comprises an interface (1206) directly connected to an external DRAM, said interface being directly accessible by the function capable of executing the non-recursive filter calculation providing the basic operation of digital signal processing at the rate of one cycle per tap.

8. A method of configuring a high-level language compiler for generating a microprocessor program used for the terminal apparatus according to claim 1, wherein at least an address register for a digital signal processor realizing the DSP function is mapped to a subset of registers for a central processing unit realizing the CPU function thereby to deliver at least an argument to said subset of the registers of said central processing unit.

9. A terminal apparatus for effecting radio communication by exchanging data with a base station, comprising:

a data processing unit (500) for executing a program stored in memory; and

a memory including an area (801) storing a program for performing the audio coding/encoding process, an area storing a program for performing the speech decoding process, an area storing a program for performing the channel decoding process, an area (803) storing a program for controlling the communication protocol with the base station, and an area storing a program for controlling the interface with the user;

wherein each of said areas of said memory is arranged in an address space of said data processing unit.

10. A terminal apparatus according to claim 9, wherein said data processing unit includes a digital signal processor for executing the audio coding process, the speech decoding process, the communication path coding process and the communication path decoding, and a central processing unit for controlling the communication protocol with the base station and also controlling the interface with the user, wherein said digital signal processor and said central processing unit are formed on a single semiconductor substrate.

11. A terminal apparatus according to claim 9 or 10, wherein said memory built in said data processing unit has said area storing a program for executing the audio coding process, said area storing a program for executing the speech decoding process, said area storing a program for executing the communication path coding, and said area storing a program for executing the communication path decoding.

12. A terminal apparatus according to any one of claims 9 and 10, wherein a memory external to said data processing unit has an area storing a program for controlling the communication protocol with the base station and an area storing a program for controlling the interface with the user.

13. A terminal apparatus according to claim 9 or 10, wherein said data processing unit includes, in the address space of said central processing unit, a serial input-output circuit for interfacing with an analog/digital converter circuit and a digital/analog converter circuit.

14. A data processing system comprising:

a digital signal processor capable of executing the non-recursive filter operation at the rate of one cycle per tap;

a central processing unit; and

a memory arranged in the address space of said central processing unit for storing a processing program of said digital signal processing unit and said central processing unit.