System with wide operand architecture and method
First Claim
1. (New) A processor comprising:
- a virtual memory addressing unit;
a data path;
a register file comprising a plurality of registers coupled to the data path;
an execution unit coupled to the data path, the execution unit capable of executing group floating-point operations in which multiple floating-point operands stored in partitioned fields of one or more of the plurality of registers are operated on to produce catenated results, wherein an elemental width of the floating-point operands is equal to or less than a width of the data path.
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Abstract
The present invention provides a system and method for expanding at least one source operand to a width greater than the width of either the general purpose register or the data path width. Operands are provided which are substantially larger than the data path width of the processor. A general purpose register is used to specify a memory address from which at least more than one, but typically several data path widths of data can be read. The data path functional unit is augmented with dedicated storage to which the memory operand is copied on an initial execution of the instruction. Further execution of the instruction or other similar instructions that specify the same memory address can read the dedicated storage to obtain the operand value. However, such reads are subject to conditions to verify that the memory operand has not been altered by intervening instructions. If the memory operand remains current, the memory operand fetch can be combined with one or more register operands in the functional unit, producing a result. The size of the result is, typically, constrained to that of a general register so that no dedicated or other special storage is required for the result.
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Citations
54 Claims
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1. (New) A processor comprising:
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a virtual memory addressing unit;
a data path;
a register file comprising a plurality of registers coupled to the data path;
an execution unit coupled to the data path, the execution unit capable of executing group floating-point operations in which multiple floating-point operands stored in partitioned fields of one or more of the plurality of registers are operated on to produce catenated results, wherein an elemental width of the floating-point operands is equal to or less than a width of the data path. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
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39. (New) A programmable processor capable of operation independent of another host processor, the programmable processor comprising:
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a virtual memory addressing unit;
a data path;
an external interface operable to receive data from an external source and communicate the received data over the data path;
a cache operable to retain data communicated between the external interface and the data path;
a register file comprising a plurality of registers coupled to the data path;
a multi-precision execution unit coupled to the data path, the multi-precision execution unit capable of executing group integer and group floating-point operations in which multiple operands stored in partitioned fields of one or more of the plurality of registers are operated on to produce catenated results that are returned to a register in the plurality of registers, wherein an elemental width of the operands is equal to or less than a width of the data path and wherein the multi-precision execution unit is capable of performing group integer operations on integer data of more than one precision. - View Dependent Claims (40, 41, 42, 43, 44, 45, 46, 47, 48, 49)
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50. (New) A programmable processor capable of operation independent of another host processor, the programmable processor comprising:
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a virtual memory addressing unit;
a data path;
an external interface operable to receive data from an external source at a rate of at least 2 gigabits/second and communicate the received data over the data path;
a cache operable to retain data communicated between the external interface and the data path;
a register file comprising a plurality of registers coupled to the data path, the plurality of registers configurable to receive and store catenated data from the data path and communicate the catenated data to the data path, wherein the elemental width of the catenated data may be any one of the following types;
8-bit, 16-bit, 32-bit and 64-bit integer type and 32-bit floating-point type;
a multi-precision execution unit coupled to the data path, the multi-precision execution unit capable of executing group integer, group floating-point and group data handling operations in which multiple operands stored in partitioned fields of one or more of the plurality of registers are operated on in parallel to produce catenated results that are returned to a register in the plurality of registers, wherein an elemental width of the operands is equal to or less than a width of the data path and wherein the multi-precision execution unit is capable of performing group integer operations on integer data of more than one precision. - View Dependent Claims (51, 52, 53, 54)
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Specification