Apparatus for dynamically adjusting CPU power consumption

• US 20040049704A1
• Filed: 12/11/2002
• Published: 03/11/2004
• Est. Priority Date: 09/09/2002
• Status: Active Grant

• Current Assignee: Quanta Computer
• Original Assignee: Quanta Computer
• Inventors: Yang, Yu-Jen, Liu, Cheng-Ting
• Granted Patent: US 7,010,704 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus for dynamically adjusting power consumption of a CPU in a computer system is described. A current flowing through the limiting resistor is detected and whether or not this current is larger than a predetermined current is determined. A warning signal is issued when the current is larger than this predetermined signal. The warning signal triggers the software framework and the hardware framework of the apparatus to issue an asynchronous operation frequency reduction instruction to the CPU of the computer system.

Claims

1. An apparatus for dynamically adjusting the power consumption of a CPU in a computer system, wherein a current flowing through a limited resistor is used to supply needs of an entire computer system, said apparatus comprising:

a current sensor for detecting said current and generating a detected signal;

a comparator for comparing said detected signal with a first predetermined value, wherein if said detected signal is larger than said first predetermined value a warning signal is generated;

a hardware framework, wherein said warning signal triggers said hardware framework to generate and send an operation frequency reduction instruction having a special frequency to said CPU; and

a software framework, wherein said warning signal triggers said software framework to perform a first rewriting process to change a set value stored in said software framework to generate and send an operation frequency reduction instruction to said CPU to reduce an operation frequency thereof, and said software framework continues to detect said detected signal and compare said detected signal with a second predetermined value, wherein if said detected signal is less than said second predetermined value, a second rewriting process is performed to change the set value stored in said software framework and remove said operation frequency reduction instruction applied to said CPU according to said second rewriting process.

2. The apparatus for dynamically adjusting power consumption according to claim 1, wherein said hardware framework comprises a frequency generator, and said frequency generator is triggered by said warning signal and generates said operation frequency reduction instruction to said CPU according to a frequency defined by said frequency generator.

3. The apparatus for dynamically adjusting power consumption according to claim 1, wherein said hardware framework comprises:

a D-type flip-flop, wherein said D-type flip-flop is triggered by said warning signal and generates a latch up signal; and

an embedded controller for receiving said latch up signal, wherein said latch up signal controls said embedded controller to perform a first rewriting process to change the set value stored in said embedded controller and said embedded controller generates and sends a first signal to the basic input and output system of said computer system to command the chipset to send said operation frequency reduction instruction to said CPU to reduce the operation frequency thereof according to said first rewriting process, and said embedded controller continues detecting said detected signal and compares said detected signal with a second predetermined value, and if said detected signal is less than said second predetermined value, said embedded controller sends a reset signal to said D-type flip-flop to remove said latch up signal and a second rewriting process is performed to change the set value stored in said embedded controller, and said embedded controller generates and sends a second signal to the basic input/output system of said computer system to command the chipset to remove said operation frequency reduction instruction applied to said CPU according to said second rewriting process.

4. The apparatus for dynamically adjusting power consumption according to claim 1, wherein said first signal and said second signal are SMI signals.

5. The apparatus for dynamically adjusting power consumption according to claim 1, wherein said first predetermined value is set according to a maximum power consumption supported by the CPU, namely, a maximum loading the CPU wants to process.

6. The apparatus for dynamically adjusting power consumption according to claim 1, wherein said second predetermined value is set according to the computer system for removing the operation frequency reduction instruction applied to the CPU

7. The apparatus for dynamically adjusting power consumption according to claim 1, wherein said operation frequency reduction instruction is STPCLK#.

8. An apparatus for dynamically adjusting power consumption of a CPU in a computer system, wherein a basic input/output system and a chipset exist in said computer system and a current flowing through a limited resistor is used to supply needs of an entire computer system, said apparatus comprising:

a current sensor for detecting said current and generating a detected signal;

a comparator for comparing said detected signal with a first predetermined value, wherein if said detected signal is larger than said first predetermined value, a warning signal is generated;

a frequency generator, wherein said frequency generator is triggered by said warning signal and generates and sends an operation frequency reduction instruction to said CPU according a frequency defined by said frequency generator;

a D-type flip-flop, wherein said D-type flip-flop is triggered by said warning signal and generates a latch up signal; and

an embedded controller for receiving said latch up signal, wherein said latch up signal commands said embedded controller to perform a first rewriting process to change the a set value stored in said embedded controller and said embedded controller generates and sends a first signal to the basic input and output system to command the chipset to send an operation frequency reduction instruction to said CPU to reduce an operation frequency thereof according to said first rewriting process, and said embedded controller keeps detecting said detected signal and compare said detected signal with a second predetermined value, wherein if said detected signal is less than said second predetermined value, said embedded controller sends a reset signal to said D-type flip-flop to remove said latch up signal, a second rewriting process is performed to change the set value stored in said embedded controller, and said embedded controller generates and sends a second signal to the basic input /output system to command the chipset to remove said operation frequency reduction instruction applied to said CPU according to said second rewriting process.

9. The apparatus for dynamically adjusting power consumption according to claim 8, wherein said first signal and said second signal are SMI signals.

10. The apparatus for dynamically adjusting power consumption according to claim 8, wherein said first predetermined value is about 90 watts.

11. The apparatus for dynamically adjusting power consumption according to claim 8, wherein said second predetermined value is about 75 watts.

12. The apparatus for dynamically adjusting power consumption according to claim 8, wherein said operation frequency reduction instruction is STPCLK#.

13. A method of dynamically adjusting the power consumption for a CPU in a computer system, wherein a basic input/output system and a chipset exist in said computer system and a current flowing through a limited resistor is used to supply needs of an entire computer system, said method comprising:

detecting said current and generating a detected signal;

comparing said detected signal with a first predetermined value, wherein if said detected signal is larger than said first predetermined value a warning signal is generated;

using said warning signal to trigger said frequency generator and generating an operation frequency reduction instruction to said CPU;

using said warning signal to trigger said D-type flip-flop and generate a latch up signal; and

using said latch up signal to control an embedded controller, wherein said embedded controller performs a first rewriting process to change a set value stored therein, said embedded controller generates a first signal to the basic input and output system to command the chipset to send an operation frequency reduction instruction to said CPU to reduce an operation frequency thereof according to said first rewriting process, and said embedded controller continues to detect said detected signal and compare said detected signal with a second predetermined value, wherein if said detected signal is less than said second predetermined value, said embedded controller sends a reset signal to said D-type flip-flop to remove said latch up signal and a second rewriting process is performed to change set value stored in said embedded controller, and said embedded controller generates a second signal to the basic input /output system to command the chipset to remove said operation frequency reduction instruction applied to said CPU according to said second rewriting process.

14. The method of dynamically adjusting power consumption according to claim 13, wherein said first signal and said second signal are SMI signals.

15. The method of dynamically adjusting power consumption according to claim 13, wherein said first predetermined value is set according to a maximum power consumption supported by the CPU, namely, a maximum loading the CPU wants to process.

16. The method of dynamically adjusting power consumption according to claim 13, wherein said first predetermined value is about 90 watts.

17. The method of dynamically adjusting power consumption according to claim 13, wherein said second predetermined value is set according to the computer system for removing the operation frequency reduction instruction applied to the CPU.

18. The method of dynamically adjusting power consumption according to claim 13, wherein said second predetermined value is about 75 watts.

19. The method of dynamically adjusting power consumption according to claim 13, wherein said work frequency reduction instruction is STPCLK#.

20. The method of dynamically adjusting power consumption according to claim 13, wherein said basic input and output system commands the chipset to send said operation frequency reduction instruction to said CPU to reduce the operation frequency thereof to about 50%, 60% or 87.5% of an original operation frequency of the CPU.