Transponder interrogators, radio frequency identification device communication systems, transponder interrogator communication methods, and radio frequency identification device communication methods

• US 20040049718A1
• Filed: 09/05/2003
• Published: 03/11/2004
• Est. Priority Date: 02/28/1998
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: David K. Ovard, George E. Pax
• Inventors: Ovard, David K., Pax, George E.
• Granted Patent: US 6,938,200 B2
• Time in Patent Office: Days
• US Class Current: 714/700
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 7/0008 General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer
• CPC Class Codes: H03M 13/33 Synchronisation based on error coding or decoding
• CPC Class Codes: H04L 7/0334 Processing of samples having at least three levels, e.g. soft decisions
• CPC Class Codes: H04L 7/046 using a dotting sequence
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

The present invention includes bit synchronizers and methods of synchronizing and calculating error. One method of synchronizing with a data signal in accordance with the present invention includes providing a data signal having a first portion and a second portion, generating a timing signal, first adjusting the timing signal during the first portion of the data signal, accumulating a history value during the first portion of the data signal, and second adjusting the timing signal during a second portion of the data signal using the history.

Claims

1. A bit synchronizer configured to generate a timing signal for sampling a data signal comprising:

an error generator configured to detect error of the timing signal with respect to the data signal and output error update signals responsive to the detection of error;

a bit clock generator configured to output the timing signal responsive to the error update signals and a plurality of history signals; and

history circuitry configured to receive the error update signals and generate a history during a first portion of the data signal and generate the history signals during a second portion of the data signal responsive to the history.

2. The bit synchronizer according to claim 1 wherein the first portion is a preamble of the data signal.

3. The bit synchronizer according to claim 2 wherein the preamble comprises alternating digital high and digital low data.

4. The bit synchronizer according to claim 1 wherein the second portion of the data signal intermittently contains insufficient timing information.

5. The bit synchronizer according to claim 4 wherein the history circuitry is configured to detect insufficient timing information.

6. The bit synchronizer according to claim 1 wherein the history circuitry is adapted to accumulate the error update signals during the first portion of the data signal.

7. The bit synchronizer according to claim 1 wherein the bit clock generator comprises:

a reference counter configured to generate a nominal frequency signal;

a reloadable counter configured to count a predetermined number of counts responsive to the nominal frequency signal; and

a count decoder configured to output plural load timing signals responsive to the count of the reloadable counter.

8. The bit synchronizer according to claim 7 wherein the reloadable counter is reloaded responsive to receiving one of the load timing signals.

9. The bit synchronizer according to claim 7 wherein the bit clock generator further comprises a multiplexer configured to select one of the history signals and error update signals for controlling the applying of load timing signals to the counter, the multiplexer being configured to select responsive to the data signal.

10. The bit synchronizer according to claim 7 wherein the bit clock generator is adapted to adjust the load timing signals responsive to the bit clock signal.

11. The bit synchronizer according to claim 7 wherein the reference counter is configured to adjust the nominal frequency signal responsive to the history signals.

12. The bit synchronizer according to claim 7 wherein the timing of the loading of the reloadable counter is responsive to the load timing signals, error update signals and history signals.

13. The bit synchronizer according to claim 1 wherein the error update signals comprise error magnitude and error direction information.

14. The bit synchronizer according to claim 1 wherein the history signals comprise history magnitude and history direction information.

15. The bit synchronizer according to claim 1 wherein the error generator comprises:

an accumulator for measuring first and second reference values of the data signal; and

a comparator configured to generate an error magnitude and an error direction signal responsive to a comparison of the first and second reference values.

16. The bit synchronizer according to claim 1 wherein the first and second reference values correspond to portions of the data signal including respective portions of a bit.

17. The bit synchronizer according to claim 1 wherein the first and second reference values correspond to portions of the data signal adjacent a transition of data from one digital value to another digital value.

18. A method of synchronizing with a data signal comprising:

providing a data signal having a first portion and a second portion;

generating a timing signal;

first adjusting the timing signal during the first portion of the data signal;

accumulating a history value during the first portion of the data signal; and

second adjusting the timing signal during a second portion of the data signal using the history.

19. The method according to claim 18 further comprising sampling the data signal according to the timing signal.

20. The method according to claim 18 wherein the first portion of the data signal comprises a preamble.

21. The method according to claim 20 wherein the preamble comprises alternating digital high and digital low values.

22. The method according to claim 18 further comprising detecting insufficient timing information within the second portion of the data signal and the second adjusting being responsive to the detecting.

23. The method according to claim 18 wherein the adjustings individually comprise adjusting at least one of frequency and phase of the timing signal.

24. The method according to claim 18 further comprising determining error of the timing signal with respect to the data signal.

25. The method according to claim 24 wherein the determining comprises:

measuring first and second reference values corresponding to respective portions of the data signal; and

comparing the first and second reference values.

26. The method according to claim 25 wherein the first and second reference values correspond to respective portions of a bit.

27. The method according to claim 25 wherein the first and second reference values correspond to portions of the data signal adjacent a transition of data from one digital value to another digital value.

28. The method according to claim 25 further comprising adjusting the phase of the timing signal responsive to the determined timing signal error and adjusting the frequency of the timing signal responsive to the history.

29. The method according to claim 24 wherein the accumulating comprises totaling the error during the first portion of the data signal.

30. The method according to claim 18 wherein the history comprises magnitude and direction information.

31. The method according to claim 24 wherein the error comprises magnitude and direction information.

32. The method according to claim 18 wherein the generating the timing signal comprises:

providing a nominal frequency signal; and

converting the nominal frequency to a bit clock signal.

33. The method according to claim 32 wherein the converting comprises:

loading a counter value; and

counting to the counter value according to the nominal frequency signal.

34. The method according to claim 33, further comprising:

determining error of the timing signal with respect to the data signal; and

adjusting the timing of the loading of the counter value responsive to one of error and the history.

35. A method of synchronizing with a data signal comprising:

providing a data signal including digital information;

deriving timing information during a first portion of the data signal;

generating a timing signal;

detecting an absence of timing information during a second portion of the data signal; and

adjusting the timing signal during the second portion of the data signal.

36. The method according to claim 35 further comprising:

determining error of the timing signal with respect to the data signal during a first portion of the data signal; and

generating a history responsive to the determining and prior to the detecting.

37. The method according to claim 36 wherein the adjusting the timing signal during the second portion of the data signal is responsive to the history.

38. The method according to claim 35 further comprising sampling the data signal according to the timing signal.

39. The method according to claim 35 wherein the first portion of the data signal comprises a preamble.

40. The method according to claim 39 wherein the preamble comprises alternating digital high and digital low values.

41. The method according to claim 35 wherein the adjusting comprises individually adjusting at least one of the frequency and the phase of the timing signal.

42. The method according to claim 36 wherein the determining comprises:

measuring first and second reference values of the data signal; and

comparing the first and second reference values.

43. The method according to claim 42 wherein the first and second reference values correspond to portions of the data signal including respective portions of a bit.

44. The method according to claim 42 wherein the first and second reference values correspond to portions of the data signal adjacent a transition of data from one digital value to another digital value.

45. The method according to claim 36 further comprising:

adjusting the phase of the timing signal responsive to the error; and

adjusting the frequency of the timing signal responsive to the history.

46. The method according to claim 36 wherein the history comprises magnitude and direction information.

47. The method according to claim 36 wherein the error comprises magnitude and direction information.

48. The method according to claim 36 wherein the generating the timing signal comprises:

providing a nominal frequency signal; and

converting the nominal frequency signal to a bit clock signal.

49. The method according to claim 48 wherein the converting comprises:

loading a counter value; and

counting to the counter value responsive to the nominal frequency signal.

50. The method according to claim 49 further comprising adjusting the timing of the loading of the counter value responsive to one of error and history.

51. A method of calculating error of a timing signal with respect to a data signal comprising:

receiving a data signal containing plural digital values;

first analyzing the data signal corresponding to a first portion of a selected digital value of the data signal;

providing a first reference value responsive to the first analyzing;

second analyzing the data signal corresponding to a second portion of the selected digital value of the data signal;

providing a second reference value responsive to the second analyzing; and

comparing the first reference value with the second reference value.

52. The method according to claim 51 further comprising generating a timing signal corresponding to the data signal.

53. The method according to claim 52 wherein the timing signal defines the first and second portions of the selected digital value of the data signal.

54. The method according to claim 52 wherein the timing signal has a frequency approximately equal to a bit rate of the data signal.

55. The method according to claim 51 wherein the first and second portions correspond to respective halves of the selected digital value.

56. The method according to claim 51 wherein the selected digital value corresponds to a bit of the data signal.

57. The method according to claim 51 wherein the selected digital value is a digital zero.

58. The method according to claim 51 wherein the first and second analyzings comprise measuring areas of the respective first and second portions of the selected digital value.

59. The method according to claim 51 wherein the comparing comprises subtracting the first and second reference values.

60. The method according to claim 52 wherein the comparing defines the error of the timing signal with respect to the data signal.

61. A method of synchronizing with a data signal comprising:

providing a data signal including a preamble and a data portion;

generating a timing signal having a phase and frequency, the generating including;

providing a nominal frequency signal; and

converting the nominal frequency signal to a bit clock signal;

sampling the data signal according to the timing signal;

determining error of the timing signal with respect to the data signal, the determining including;

measuring first and second reference values of the data signal; and

comparing the first and second reference values;

first adjusting the phase of the timing signal during the preamble of the data signal, the first adjusting being responsive to the determining;

accumulating a history during the preamble and responsive to the determining;

adjusting the frequency of the nominal frequency signal using the history;

detecting an absence of timing information within the data signal; and

following the detecting, second adjusting the phase of the timing signal using the history during the data portion of the data signal.