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Failure analysis system, failure analysis method, a computer program product and a manufacturing method for a semiconductor device

  • US 20040049722A1
  • Filed: 06/30/2003
  • Published: 03/11/2004
  • Est. Priority Date: 09/09/2002
  • Status: Abandoned Application
First Claim
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1. A failure analysis system, comprising:

  • a chip position calculation module configured to calculate fault chip positions of a plurality of circuit blocks in a chip region based on layout information on the circuit blocks positioned in the chip region and fault information on the circuit blocks;

    a wafer position calculation module configured to calculate fault wafer positions in a wafer based on the fault chip positions and position information showing a chip region layout in a wafer plane; and

    a mapping module configured to perform a mapping display of the fault wafer positions in accordance with physical coordinates on the wafer plane.

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