TEST STRUCTURES FOR ON-CHIP REAL-TIME RELIABILITY TESTING

• US 20040051553A1
• Filed: 09/13/2002
• Published: 03/18/2004
• Est. Priority Date: 09/13/2002
• Status: Active Grant

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (GlobalFoundries, Inc.)
• Inventors: Manna, Indrajit, Foo, Lo Keng, Qiang, Guo, Xu, Zeng
• Granted Patent: US 6,724,214 B2
• Time in Patent Office: Days
• US Class Current: 324/766
• CPC Class Codes: G01R 31/129 of components or parts made of semiconducting materials; of LV components or parts G01R31/18 takes precedence
• CPC Class Codes: G01R 31/2642 Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests
• CPC Class Codes: G01R 31/2858 Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/3004 Current or voltage test
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

Described is a system with three on chip monitoring test structures. If any of the three test structures indicates an end of life failure, a bit will be set indicating that the IC is near failure and should be replaced. This is done prior to actual device failure and will eliminate down time of the system where this IC is used. The first test structure monitors hot carrier degradation and is comprised of two ring oscillators. One is subjected to hot carrier effects (degrading ring oscillator) and the other is not subjected to hot carrier effects (non-degrading ring oscillator). Initially, both ring oscillators will each have fixed frequencies, but as the device ages, hot carrier effects degrade the degrading ring counter. Using the non-degrading ring oscillator, the degradation can be quantified and flag a failure. The second test structure monitors TDDB degradation. A plurality of N parallel connected capacitors have a stress voltage applied to them such that the time to failure of the first capacitor is the same time to failure experienced by 0.1 percentile of gates under normal usage. Breakdown of a capacitor is observed by a drop in the resistance of the structure and is used to trigger a bit indicating a TDDB end of life signal. The third test structure monitors electromigration degradation. M minimum width metal lines are connected in parallel. A current is applied to them such that the time to failure of all metal lines is the same as the time to failure experienced by 0.1 percentile of minimum width metal lines under normal usage. Breakdown of a metal line is observed by an increase in the resistance of the structure and is used to trigger a bit indicating an electromigration end of life signal. 0.1 percentile is given as an example and can be varied depending upon the users definition of device lifetime.

Claims

1. A method for indicating end-of-lifetime in an integrated circuit comprising:

predicting hot carrier injection failure;

predicting gate oxide TDDB failure;

predicting electromigration failure; and

indicating when either of said hot carrier injection failure, said gate oxide TDDB failure, or said electromigration failure occurs.

2. The method according to claim 1 wherein said predicting hot carrier injection failure is accomplished by measuring the frequency of a ring oscillator being degraded by hot carrier injection and indicating failure when said frequency drops below a given threshold.

3. The method according to claim 2 wherein said frequency of said ring oscillator is measured by counting pulses from said ring oscillator over a fixed interval.

4. The method according to claim 3 wherein said fixed interval is determined by a non-degrading ring oscillator.

5. The method according to claim 3 wherein said fixed interval is determined by a non-degrading ring oscillator and by dividing the frequency of said non-degraded ring oscillator.

6. The method according to claim 1 wherein said predicting gate oxide TDDB failure is accomplished by measuring the resistance of a plurality of capacitors being exercised by a stress voltage and by indicating failure when said resistance of said plurality of capacitors drops below a given threshold.

7. The method according to claim 6 wherein said resistance of said plurality of capacitors is determined by application of a sense voltage in series with a large resistor to said plurality of capacitors and measuring the voltage across said plurality of capacitors.

8. The method according to claim 7 wherein said sense voltage is about equal to the supply voltage of said integrated circuit.

9. The method according to claim 6 wherein said stress voltage is between about 1.2 and 1.8 times the supply voltage of said integrated circuit.

10. The method according to claim 6 wherein the number of said plurality of capacitors and the magnitude of said sense voltage are chosen by translating the use condition Weibull distribution so that the first failure reflects a chosen percentile of the typical device lifetime.

11. The method according to claim 1 wherein said predicting electromigration failure is accomplished by measuring the resistance of a plurality of parallel connected, minimum width, metal lines being exercised by a stress voltage and by indicating failure when said resistance of said plurality of parallel connected, minimum width, metal lines rises above a given threshold.

12. The method according to claim 11 wherein said resistance of said plurality of parallel connected, minimum width, metal lines is determined by application of a sense voltage in series with a small resistor to said plurality of parallel connected, minimum width, metal lines and measuring the voltage across said plurality of parallel connected, minimum width, metal lines.

13. The method according to claim 12 wherein said sense voltage is about one-half the supply voltage of said integrated circuit.

14. The method according to claim 11 wherein said stress voltage is between about 0.5 and 1.0 times the supply voltage of said integrated circuit.

15. The method according to claim 11 wherein the number of said plurality of metal lines and the magnitude of said sense voltage are chosen by translating the use condition lognormal distribution so that the first failure reflects a chosen percentile of the typical device lifetime.

16. A method for indicating end-of-lifetime in an integrated circuit comprising:

predicting hot carrier injection failure by measuring the frequency of a ring oscillator being degraded by hot carrier injection and indicating failure when said frequency drops below a given threshold;

predicting gate oxide TDDB failure by measuring the resistance of a plurality of capacitors being exercised by a stress voltage and by indicating failure when said resistance of said plurality of capacitors drops below a given threshold;

predicting electromigration failure by measuring the resistance of a plurality of parallel connected, minimum width, metal lines being exercised by a stress voltage and by indicating failure when said resistance of said plurality of parallel connected, minimum width, metal lines rises above a given threshold; and

indicating when either of said hot carrier injection failure, said gate oxide TDDB failure, or said electromigration failure occurs.

17. The method according to claim 16 wherein said frequency of said ring oscillator is measured by counting said pulses from said ring oscillator over a fixed interval.

18. The method according to claim 17 wherein said fixed interval is determined by a non-degrading ring oscillator.

19. The method according to claim 17 wherein said fixed interval is determined by a non-degrading ring oscillator and by dividing the frequency of said non-degraded ring oscillator.

20. The method according to claim 16 wherein said resistance of said plurality of capacitors is determined by application of a sense voltage in series with a large resistor to said plurality of capacitors and measuring the voltage across said plurality of capacitors.

21. The method according to claim 20 wherein said sense voltage is about equal to the supply voltage of said integrated circuit.

22. The method according to claim 16 wherein said stress voltage is between about 1.2 and 1.8 times the supply voltage of said integrated circuit.

23. The method according to claim 16 wherein said resistance of said plurality of parallel connected, minimum width, metal lines is determined by application of a sense voltage in series with a small resistor to said plurality of parallel connected, minimum width, metal lines and measuring the voltage across said plurality of parallel connected, minimum width, metal lines.

24. The method according to claim 23 wherein said sense voltage is about one-half the supply voltage of said integrated circuit.

25. The method according to claim 16 wherein said stress voltage is between about 0.5 and 1.0 times the supply voltage of said integrated circuit.

26. The method according to claim 16 wherein the number of said plurality of capacitors and the magnitude of said sense voltage are chosen by translating the use condition Weibull distribution so that the first failure reflects a chosen percentile of the typical device lifetime.

27. The method according to claim 16 wherein the number of said plurality of metal lines and the magnitude of said sense voltage are chosen by translating the use condition lognormal distribution so that the first failure reflects a chosen percentile of the typical device lifetime.

28. A device for indicating end-of-lifetime in an integrated circuit comprising:

a circuit for predicting hot carrier injection failure;

a circuit for predicting gate oxide TDDB failure;

a circuit for predicting electromigration failure; and

a circuit for indicating when either of said hot carrier injection failure, said gate oxide TDDB failure, or said electromigration failure occurs.

29. The device according to claim 28 wherein said circuit for predicting hot carrier injection failure is comprised of:

a ring oscillator that is degrading due to hot carrier injection producing a first clock signal;

a ring oscillator that is not degrading due to hot carrier injection producing a second clock signal;

a 2^k frequency divider where k is an integer;

a binary counter having a multi-bit output; and

a binary comparator;

wherein;

said first clock signal is applied to the input of said binary counter;

said second clock signal is applied to the input of said 2^k frequency divider thereby outputting a third clock signal with a frequency that is ½

^k times the frequency of the second clock signal;

said third clock signal initializes and enables said binary counter and said binary comparator;

said multi-bit output of said binary counter is applied to said binary comparator; and

said binary comparator compares said multi-bit output against a fixed binary value thereby determining if said hot carrier injection failure has occurred.

30. The device according to claim 28 wherein said circuit for predicting gate oxide TDDB failure is comprised of:

a capacitor bank comprised of a plurality of parallel-connected capacitors having terminals A and B;

a first resistor electrically connected between said terminal B and a circuit common;

a stress voltage source connected by a first switch to said terminal A;

a sense voltage source connected by a second switch in series with a second resistor to said terminal A; and

a third switch connecting said terminal A to the input of an inverter;

wherein;

said capacitor bank is stressed by closing said first switch and opening said second switch and said third switch; and

said predicting of gate oxide TDDB failure is determined by opening said first switch and closing said second switch and said third switch and observing the logic state of the output of said inverter wherein if said logic level of said output of said inverter is high, said gate oxide TDDB failure has occurred.

31. The device according to claim 30 wherein the number of said plurality of capacitors and the magnitude of said sense voltage are chosen by translating the use condition Weibull distribution so that the first failure reflects a chosen percentile of the typical device lifetime.

32. The device according to claim 28 wherein said circuit for predicting electromigration failure is comprised of:

a metal line bank comprised of a plurality of parallel connected, minimum width metal lines having terminals A and B wherein said terminal B is electrically connected to a circuit common;

a stress voltage source connected by a first switch to said terminal A;

a sense voltage source connected by a second switch in series with a second resistor to said terminal A; and

a third switch connecting said terminal A to the input of a latch;

wherein;

said metal line bank is stressed by closing said first switch and opening said second switch and said third switch; and

said predicting of electromigration failure is determined by opening said first switch and closing said second switch and said third switch and observing the logic state of the output of said latch wherein if said logic level of said output of said latch is high, said electromigration failure has occurred.

33. The device according to claim 32 wherein the number of said plurality of metal lines and the magnitude of said sense voltage are chosen by translating the use condition lognormal distribution so that the first failure reflects a chosen percentile of the typical device lifetime.