Process monitor based keeper scheme for dynamic circuits

• US 20040051562A1
• Filed: 09/17/2002
• Published: 03/18/2004
• Est. Priority Date: 09/17/2002
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Gauthier, Claude R., Desai, Shaishav A.
• Granted Patent: US 6,894,528 B2
• Time in Patent Office: Days
• US Class Current: 326/98
• CPC Class Codes: H03K 19/0963 using transistors of complementary type H03K19/0966 takes precedence

Abstract

An invention is disclosed for a process monitor based keeper scheme for dynamic circuits. A semiconductor die having a process monitor based keeper scheme of the embodiments of the present invention generally includes a plurality of dynamic circuits, each having an adaptive keeper circuit capable of being adjusted based on a bit code. In addition, a plurality of process monitors is included. Each process monitor is disposed within a corresponding die block, which defines a local area of the die. The process monitors are capable of detecting process corner data for the corresponding die block. In communication with each process monitor and the plurality of dynamic circuits is a test processor unit. The test processor unit obtains process corner data for each die block from the process monitor disposed within the die block, and provides a bit code based on the process corner data to the dynamic circuits disposed within the die block.

Claims

1. A semiconductor die having adaptive keeper logic, comprising:

a plurality of dynamic circuits, each dynamic circuit including an adaptive keeper circuit capable of being adjusted based on a bit code;

a plurality of process monitors, each process monitor disposed within a corresponding die block defining a local area of the die, each process monitor capable of detecting process corner data for the corresponding die block; and

a test processor unit in communication with each process monitor and the plurality of dynamic circuits, the test processor unit being capable of obtaining process corner data for each die block from the process monitor disposed within the die block and providing a bit code based on the process corner data to dynamic circuits disposed within the same die block.

2. A semiconductor die as recited in claim 1, wherein each adaptive keeper circuit includes at least one feedback bit line that receives a portion of the bit code, the feedback bit line controlling current flow to an internal dynamic node.

3. A semiconductor die as recited in claim 2, wherein each adaptive keeper circuit further includes a first keeper transistor and at least one secondary keeper transistor in parallel with the first keeper transistor.

4. A semiconductor die as recited in claim 3, wherein the first keeper transistor and the secondary keeper transistor being in electrical communication with a power supply, the first keeper transistor further being in electrical communication with an internal dynamic node.

5. A semiconductor die as recited in claim 4, wherein each adaptive keeper circuit further includes at least one feedback transistor in electrical communication with the at least one secondary transistor, the feedback transistor controlling current flow between the secondary transistor and the internal dynamic node.

6. A semiconductor die as recited in claim 5, wherein the at least one feedback transistor controls current flow between the secondary transistor and the internal dynamic node based on a state of the feedback bit line.

7. A semiconductor die as recited in claim 6, wherein the test processor unit translates the process corer data into the bit code using a lookup function.

8. An adaptive keeper circuit disposed within a die block defining a local area of a die, comprising:

a first keeper transistor having a first terminal in electrical communication with a power supply and a second terminal in electrical communication with an internal dynamic node;

a second keeper transistor configured in parallel to the first keeper transistor, the second keeper transistor having a first terminal in electrical communication with the power supply; and

a feedback bit line configured to control current flow between the second keeper transistor and the internal dynamic node based on a state of the feedback bit line, the state of the feedback bit line being based on a process corner characteristic the die block.

9. An adaptive keeper circuit as recited in claim 8, further comprising a feedback transistor having a first terminal in electrical communication with the second keeper transistor, a second terminal in electrical communication with the internal dynamic node, and a gate coupled to the feedback bit line.

10. An adaptive keeper circuit as recited in claim 9, wherein the feedback transistor controls current flow between the second keeper transistor and the internal dynamic node based on a state of the feedback bit line.

11. An adaptive keeper circuit as recited in claim 8, further comprising a plurality of incremental keeper transistors, each incremental keeper transistor configured in parallel to the first keeper transistor, each incremental keeper transistor having a first terminal in electrical communication with the power supply.

12. An adaptive keeper circuit as recited in claim 11, further comprising a plurality of feedback bit lines each corresponding to a particular incremental keeper transistor of the plurality of incremental transistors, each feedback bit line configured to control current flow between the corresponding incremental keeper transistor and the internal dynamic node based on a state of the feedback bit line.

13. An adaptive keeper circuit as recited in claim 12, wherein the state of each feedback bit line of the plurality of feedback bit lines is based on process corner characteristics of the die block.

14. An adaptive keeper circuit as recited in claim 13, further comprising a plurality of feedback transistors that control current flow between corresponding incremental keeper transistors of the plurality of incremental keeper transistors and the internal dynamic node.

15. An adaptive keeper circuit as recited in claim 14, wherein a gate of each feedback transistor of the plurality of feedback transistors is coupled to a corresponding bit line of the plurality of bit lines.

16. A method for optimizing a keeper circuit for use in a dynamic circuit, comprising the operations of:

defining a plurality of die blocks defining a local area of the die;

obtaining process corner data for each die block;

translating the process corner data for each die block into a corresponding bit code, the bit code indicating a process corner of the die block; and

adding particular secondary keeper transistors to a first keeper transistor, the particular secondary keeper transistors being selected using the bit code.

17. A method as recited in claim 16, wherein the secondary keeper transistors are added to the first keeper transistor utilizing corresponding feedback transistors, each feedback transistor having a gate coupled to a bit of the bit code.

18. A method as recited in claim 17, wherein the process corner data is obtained utilizing process monitors, each process monitor being disposed within a corresponding die block.

19. A method as recited in claim 18, wherein each process monitor comprises a ring oscillator coupled to a counter.

20. A method as recited in claim 19, wherein the process corner data is a digital value provided from an output of the counter.