Differential readout from pixels in CMOS sensor

• US 20040051802A1
• Filed: 08/29/2002
• Published: 03/18/2004
• Est. Priority Date: 08/29/2002
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Inventors: Krymski, Alexander
• Granted Patent: US 7,375,748 B2
• Time in Patent Office: Days
• US Class Current: 348/308
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/63 applied to dark current
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 3/1568 for disturbance correction or prevention within the image-sensor, e.g. biasing, blooming, smearing correction circuits H04N25/62

Abstract

The present invention provides an improved pixel readout circuit that compensates for common mode noise during a read out operation. This is accomplished by using a differential readout of the signal and reset value from the desired pixel compared with the reset value from a reference pixel. In this manner common mode noise can be offset and therefore minimized. In one embodiment of the invention, the reference pixel is the nearest neighbor pixel in the same row. In another embodiment, the reference pixel is the nearest neighboring pixel in a different row.

Claims

1. A method of operating an imaging pixel array of an image sensor, said method comprising:

sampling a reset and a charge accumulated signal from a desired pixel;

sampling a reset and a comparison signal from a reference pixel, wherein said reference pixel is a desired pixel at a different time; and

using said reset and comparison signals from said reference pixel to offset noise from said desired pixel.

2. The method of claim 1, wherein said signal from said desired pixel is sampled simultaneously with said reset signal of said reference pixel.

3. The method of claim 2, wherein said charge accumulated signal from said desired pixel is simultaneously sampled with said comparison signal of said reference pixel

4. The method of claim 3, wherein said reference pixel is in a different column from said desired pixel.

5. The method of claim 4, wherein said reference pixel is in the same row as said desired pixel.

6. The method of claim 5, wherein said reference pixel is the nearest neighbor of said desired pixel.

7. The method of claim 3, wherein said reference pixel is in a different row from said desired pixel.

8. The method of claim 7, wherein said reference pixel is in the same column as said desired pixel.

9. The method of claim 8, wherein said reference pixel is the nearest neighbor of said desired pixel.

10. The method of claim 5, wherein said sampling further comprises:

enabling a reset voltage to charge a respective Node A of said desired and reference pixel;

sampling said Node A of said desired pixel and storing as said reset signal of said desired pixel;

sampling said Node A of said reference pixel and storing as said reset signal of said reference pixel;

enabling a photodiode of said desired pixel to charge Node A of said desired pixel;

sampling said Node A of said desired pixel and storing as said charge accumulated signal of said desired pixel; and

sampling said Node A of said reference pixel and storing as said comparison signal of said reference pixel.

11. The method of claim 8, wherein said sampling further comprises:

enabling a reset voltage to charge a respective Node A of said desired and reference pixel;

sampling said Node A of said desired pixel and storing as said reset signal of said desired pixel;

sampling said Node A of said reference pixel and storing as said reset signal of said reference pixel;

enabling a photodiode of said desired pixel to charge Node A of said desired pixel;

sampling said Node A of said desired pixel and storing as said charge accumulated signal of said desired pixel; and

sampling said Node A of said reference pixel and storing as said comparison signal of said reference pixel.

12. The method of claim 8, wherein said sampling further comprises:

sampling said Node A of said desired pixel and storing as said charge accumulated signal of said desired pixel;

sampling said Node A of said reference pixel and storing as said comparison signal of said reference pixel;

enabling a reset voltage to charge a Node A of said desired pixel;

sampling said Node A of said desired pixel and storing as said reset signal of said desired pixel; and

sampling said Node A of said reference pixel and storing as said reset signal of said reference pixel.

13. The method of claim 10, wherein said using further comprises:

determining a differential signal using said reset signal and charge accumulated signal of said desired pixel and said reset signal and comparison signal of said reference pixel.

14. The method of claim 11, wherein said using further comprises:

determining a differential signal using said reset signal and charge accumulated signal of said desired pixel and said reset signal and comparison signal of said reference pixel.

15. The method of claim 12, wherein said using further comprises:

determining a differential signal using said reset signal and charge accumulated signal of said desired pixel and said reset signal and comparison signal of said reference pixel.

16. A method of operating an imaging pixel array of an image sensor, said method comprising:

sampling a reset and a charge accumulated signal from a desired circuit having a shared floating diffusion node;

sampling a reset and a comparison signal from a reference circuit having a shared floating diffusion node, wherein said reference circuit is a desired circuit at a different time; and

using said reset and comparison signals from said reference circuit to offset noise from said desired circuit.

17. The method of claim 16, wherein said signal from said desired circuit is sampled simultaneously with said reset signal of said reference circuit.

18. The method of claim 17, wherein said charge accumulated signal from said desired circuit is simultaneously sampled with said comparison signal of said reference circuit

19. The method of claim 18, wherein said reference circuit is in a different column from said desired circuit.

20. The method of claim 19, wherein said reference circuit is in the same row as said desired circuit.

21. The method of claim 20, wherein said reference circuit is the nearest neighbor of said desired circuit.

22. The method of claim 18, wherein said reference circuit is in a different row from said desired circuit.

23. The method of claim 22, wherein said reference circuit is in the same column as said desired circuit.

24. The method of claim 23, wherein said reference circuit is the nearest neighbor of said desired circuit.

25. The method of claim 20, wherein said sampling further comprises:

enabling a reset voltage to charge said respective shared floating diffusion node of said desired and reference circuit;

sampling said shared floating diffusion node of said desired circuit and storing as said reset signal of said desired circuit;

sampling said shared floating diffusion node of said reference circuit and storing as said reset signal of said reference circuit;

enabling a photodiode of said desired circuit to charge shared floating diffusion node of said desired circuit;

sampling said shared floating diffusion node of said desired circuit and storing as said charge accumulated signal of said desired circuit; and

sampling said shared floating diffusion node of said reference circuit and storing as said comparison signal of said reference circuit.

26. The method of claim 23, wherein said sampling further comprises:

enabling a reset voltage to charge said respective shared floating diffusion node of said desired and reference circuit;

sampling said shared floating diffusion node of said desired circuit and storing as said reset signal of said desired circuit;

sampling said shared floating diffusion node of said reference circuit and storing as said reset signal of said reference circuit;

enabling a photodiode of said desired circuit to charge shared floating diffusion node of said desired circuit;

sampling said shared floating diffusion node of said desired circuit and storing as said charge accumulated signal of said desired circuit; and

sampling said shared floating diffusion node of said reference circuit and storing as said comparison signal of said reference circuit.

27. The method of claim 23, wherein said sampling further comprises:

sampling said shared floating diffusion node of said desired circuit and storing as said charge accumulated signal of said desired circuit;

sampling said shared floating diffusion node of said reference circuit and storing as said comparison signal of said reference circuit;

enabling a reset voltage to charge shared floating diffusion node of said desired circuit;

sampling said shared floating diffusion node of said desired circuit and storing as said reset signal of said desired circuit; and

sampling said shared floating diffusion node of said reference circuit and storing as said reset signal of said reference circuit.

28. The method of claim 25, wherein said using further comprises:

determining a differential signal using said reset signal and charge accumulated signal of said desired circuit and said reset signal and comparison signal of said reference circuit.

29. The method of claim 26, wherein said using further comprises:

determining a differential signal using said reset signal and charge accumulated signal of said desired circuit and said reset signal and comparison signal of said reference circuit.

30. The method of claim 27, wherein said using further comprises:

determining a differential signal using said reset signal and charge accumulated signal of said desired circuit and said reset signal and comparison signal of said reference circuit.

31. An image sensor, comprising:

a desired pixel for generating a reset and charge accumulation signal;

a reference pixel for generating a reset signal and comparison signal;

a circuit for sampling and holding said reset and charge accumulated signals generated by said desired pixel and said reset and comparison signals generated by said reference pixel; and

a combining circuit for generating an output based on combination of said reset and charge accumulated signals generated by said desired pixel and said reset and comparison signals generated by said reference pixel.

32. The sensor of claim 31, wherein said circuit for sampling and holding is adapted to simultaneously sample and hold said reset signal of said desired pixel and said reset signal of said reference circuit, and simultaneously samples and holds said charge accumulated signal of said desired pixel and comparison signal of said reference circuit.

33. The sensor of claim 32, wherein said desired pixel is in a same column of said reference pixel.

34. The sensor of claim 33, wherein said desired pixel is the nearest neighbor of said reference pixel.

35. The sensor of claim 34, wherein said desired pixel is in the row below said reference pixel.

36. The sensor of claim 32, wherein said desired pixel is in a same row of said reference pixel.

37. The sensor of claim 36, wherein said desired pixel is the nearest neighbor of said reference pixel.

38. An image sensor, comprising:

a desired circuit having a shared floating diffusion node for generating a reset and charge accumulation signal;

a reference circuit having a shared floating diffusion node for generating a reset signal and comparison signal;

a circuit for sampling and holding said reset and charge accumulated signals generated by said desired circuit and said reset and comparison signals generated by said reference circuit; and

a combining circuit for generating an output based on combination of said reset and charge accumulated signals generated by said desired circuit and said reset and comparison signals generated by said reference circuit.

39. The sensor of claim 38, wherein said circuit for sampling and holding is adapted to simultaneously sample and hold said reset signal of said desired circuit and said reset signal of said reference circuit, and simultaneously samples and holds said charge accumulated signal of said desired circuit and comparison signal of said reference circuit.

40. The sensor of claim 39, wherein said desired circuit is in a same column of said reference circuit.

41. The sensor of claim 40, wherein said desired circuit is the nearest neighbor of said reference circuit.

42. The sensor of claim 41, wherein said desired circuit is in the row below said reference circuit.

43. The sensor of claim 39, wherein said desired circuit is in a same row of said reference circuit.

44. The sensor of claim 43, wherein said desired circuit is the nearest neighbor of said reference circuit.

45. A circuit for sampling and holding signals from a desired and reference pixel, comprising:

a first sample and hold circuit to store a first and second signal from a desired pixel, said first circuit adapted to be coupled with a first column line; and

a second sample and hold circuit to store a third and fourth signal from a reference pixel, said second circuit adapted to be coupled with a second column line.

46. The circuit of claim 45, where said first sample and hold circuit further comprises:

a sample and hold reset circuit to store a desired pixel reset signal as said first signal from said desired pixel; and

a sample and hold signal circuit to store a desired pixel charge integrated signal as said second signal from said desired pixel.

47. The circuit of claim 45, where said second sample and hold circuit further comprises:

a second sample and hold reset circuit to store a reference pixel reset signal as said third signal from said reference pixel; and

a second sample and hold signal circuit to store a reference pixel comparison signal as said fourth signal from said desired pixel.

48. The circuit of claim 47, wherein said first and second sample and hold circuits are adapted to simultaneously sample and hold said reset signals of said desired pixel and said reset signal of said reference circuit, and said first and second sample and hold circuits are adapted to simultaneously sample and hold said comparison signal of said reference circuit and said charge accumulated signal of said desired pixel.

49. The circuit of claim 47, where said first sample and hold circuit further comprises:

a differential amplifier circuit for generating a differential output of said first and second stored signal.

50. The circuit of claim 49, where said second sample and hold circuit further comprises:

a differential amplifier circuit for generating a differential output of said third and fourth stored signal.

51. A circuit for sampling and holding signals from a desired and reference circuit having a shared floating diffusion node, comprising:

a first sample and hold circuit to store a first and second signal from a desired circuit having a shared floating diffusion node, said first circuit adapted to be coupled with a first column line; and

a second sample and hold circuit to store a third and fourth signal from a reference circuit having a shared floating diffusion node, said second circuit adapted to be coupled with a second column line.

52. The circuit of claim 51, where said first sample and hold circuit further comprises:

a sample and hold reset circuit to store a desired circuit reset signal as said first signal from said desired circuit; and

a sample and hold signal circuit to store a desired circuit charge integrated signal as said second signal from said desired circuit.

53. The circuit of claim 51, where said second sample and hold circuit further comprises:

a second sample and hold reset circuit to store a reference circuit reset signal as said third signal from said reference circuit; and

a second sample and hold signal circuit to store a reference circuit comparison signal as said fourth signal from said desired circuit.

54. The circuit of claim 53, wherein said first and second sample and hold circuits are adapted to simultaneously sample and hold said reset signals of said desired circuit and said reset signal of said reference circuit, and said first and second sample and hold circuits are adapted to simultaneously sample and hold said comparison signal of said reference circuit and said charge accumulated signal of said desired circuit.

55. The circuit of claim 53, where said first sample and hold circuit further comprises:

a differential amplifier circuit for generating a differential output of said first and second stored signal.

56. The circuit of claim 55, where said second sample and hold circuit further comprises:

a differential amplifier circuit for generating a differential output of said third and fourth stored signal.

57. A semiconductor chip, comprising:

pixel image sensor, comprising;

a desired pixel for generating a reset and charge accumulation signal;

a reference pixel for generating a reset signal and comparison signal;

a circuit for sampling and holding said reset and charge accumulated signals generated by said desired pixel and said reset and comparison signals generated by said reference pixel; and

a combining circuit for generating an output based on combination of said reset and charge accumulated signals generated by said desired pixel and said reset and comparison signals generated by said reference pixel.

58. The chip of claim 57, wherein said circuit for sampling and holding is adapted to simultaneously sample and hold said reset signal of said desired pixel and said reset signal of said reference circuit, and simultaneously samples and holds said charge accumulated signal of said desired pixel and comparison signal of said reference circuit.

59. The chip of claim 58, wherein said desired pixel is in a same column of said reference pixel.

60. The chip of claim 59, wherein said desired pixel is the nearest neighbor of said reference pixel.

61. The chip of claim 60, wherein said desired pixel is in the row below said reference pixel.

62. The chip of claim 58, wherein said desired pixel is in a same row of said reference pixel.

63. The chip of claim 62, wherein said desired pixel is the nearest neighbor of said reference pixel.

64. A processor system, comprising:

a central processing unit;

pixel image sensor coupled to said central processing unit, comprising;

a desired pixel for generating a reset and charge accumulation signal;

a reference pixel for generating a reset signal and comparison signal;

a circuit for sampling and holding said reset and charge accumulated signals generated by said desired pixel and said reset and comparison signals generated by said reference pixel; and

a combining circuit for generating an output based on combination of said reset and charge accumulated signals generated by said desired pixel and said reset and comparison signals generated by said reference pixel.

65. The system of claim 64, wherein said circuit for sampling and holding is adapted to simultaneously sample and hold said reset signal of said desired pixel and said reset signals of said reference circuit, and simultaneously samples and holds said charge accumulated signal of said desired pixel and comparison signal of said reference circuit.

66. The system of claim 65, wherein said desired pixel is in a same column of said reference pixel.

67. The system of claim 66, wherein said desired pixel is the nearest neighbor of said reference pixel.

68. The system of claim 67, wherein said desired pixel is in the row below said reference pixel.

69. The system of claim 65, wherein said desired pixel is in a same row of said reference pixel.

70. The system of claim 69, wherein said desired pixel is the nearest neighbor of said reference pixel.