Memory cell and method for forming the same
First Claim
1. A semiconductor structure formed on a surface of a substrate, comprising:
- an active region formed in the substrate;
an epitaxial post formed on the surface of the substrate over the active region, the epitaxial post having at least one surface extending outwardly from the surface of the substrate and further having a surface opposite of the surface of the substrate;
a gate structure formed adjacent to at least a portion of all the outwardly extending surfaces of the epitaxial post; and
a capacitor formed on an exposed surface of the epitaxial post.
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Accused Products
Abstract
A semiconductor memory cell structure and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, an epitaxial post formed on the surface of the substrate over the active region. The epitaxial post has at least one surface extending outwardly from the surface of the substrate and another surface opposite of the surface of the substrate. A gate structure is formed adjacent to at least a portion of all the outwardly extending surfaces of the epitaxial post, and a capacitor formed on an exposed surface of the epitaxial post.
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Citations
49 Claims
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1. A semiconductor structure formed on a surface of a substrate, comprising:
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an active region formed in the substrate;
an epitaxial post formed on the surface of the substrate over the active region, the epitaxial post having at least one surface extending outwardly from the surface of the substrate and further having a surface opposite of the surface of the substrate;
a gate structure formed adjacent to at least a portion of all the outwardly extending surfaces of the epitaxial post; and
a capacitor formed on an exposed surface of the epitaxial post. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory cell formed on a substrate having a surface, comprising:
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an active region formed in the substrate;
a vertical transistor formed in an epitaxial post formed on the substrate surface and extending from the surface of the substrate, the vertical transistor further having a gate formed around a perimeter of the epitaxial post; and
a capacitor formed on the vertical transistor. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A memory array formed on a surface of a substrate, comprising:
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a plurality of active regions formed in the surface of the substrate;
a plurality of memory cell pairs formed in a respective active region, each of the memory cell pairs comprising first and second memory cells, each cell having a vertical transistor having a conductive channel with a first end proximate to the surface of the substrate and a second end opposite the first end, a capacitor formed on the vertical transistor proximate the second end of the channel, and a diffusion region interposed between the capacitor and the second end of the channel of the vertical transistor. - View Dependent Claims (17, 18, 19, 20)
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21. A memory device having an address bus and a data terminal, comprising:
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an array of memory cells formed on a substrate including silicon, the memory cells arranged in rows and columns, each of the rows having a word line and each of the columns having a bit line;
a row address circuit coupled to the address bus for activating the word line in the array corresponding to a row address applied to the row address circuit through the address bus;
a column address circuit coupled to the address bus for coupling an I/O line for the array to the bit line corresponding to a column address applied to the column address circuit through the address bus; and
a sense amplifier having an input coupled to a data line and an output coupled to the data terminal of the memory device, wherein each memory cell comprises;
an active region formed in the substrate;
an epitaxial post formed on the surface of the substrate over the active region, the epitaxial post having at least one surface extending outwardly from the surface of the substrate and further having a surface opposite of the surface of the substrate;
a transfer gate formed adjacent to at least a portion of all the outwardly extending surfaces of the epitaxial post; and
a memory cell capacitor formed on an exposed surface of the epitaxial post. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28)
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29. A computer system, comprising:
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a processor having a processor bus;
an input device coupled to the processor through the processor bus and adapted to allow data to be entered into the computer system;
an output device coupled to the processor through the processor bus and adapted to allow data to be output from the computer system; and
a memory device coupled to the processor through the processor bus, the memory device comprising;
an array of memory cells formed on a substrate including silicon, the memory cells arranged in rows and columns, each of the rows having a word line and each of the columns having a bit line;
a row address circuit coupled to the address bus for activating the word line in the array corresponding to a row address applied to the row address circuit through the address bus;
a column address circuit coupled to the address bus for coupling an I/O line for the array to the bit line corresponding to a column address applied to the column address circuit through the address bus; and
a sense amplifier having an input coupled to a data line and an output coupled to the data terminal of the memory device, wherein each memory cell comprises;
an active region formed in the substrate;
an epitaxial post formed on the surface of the substrate over the active region, the epitaxial post having at least one surface extending outwardly from the surface of the substrate and further having a surface opposite of the surface of the substrate;
a transfer gate formed adjacent to at least a portion of all the outwardly extending surfaces of the epitaxial post; and
a memory cell capacitor formed on an exposed surface of the epitaxial post. - View Dependent Claims (30, 31, 32, 33, 34, 35, 36)
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37. A method for forming a semiconductor structure on a surface of a substrate, comprising:
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forming an active region in the substrate;
forming an epitaxial post on the substrate over the active region, the epitaxial post having at least one surface extending outwardly from the surface of the substrate and further having a surface opposite of the surface of the substrate;
forming a gate structure adjacent to at least a portion of all the outwardly extending surface of the epitaxial post; and
forming a capacitor on the exposed surface of the epitaxial post. - View Dependent Claims (38, 39, 40, 41, 42)
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43. A method for forming pair of memory cells on a surface of the substrate, comprising:
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forming an active region in the substrate;
forming a vertical transistor in an epitaxial post formed on the substrate surface and extending from the surface of the substrate, the vertical transistor further having a gate formed around a perimeter of the epitaxial post; and
forming a capacitor on the vertical transistor. - View Dependent Claims (44, 45, 46, 47, 48, 49)
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Specification