Conductive structure fabrication process using novel layered structure and conductive structure fabricated thereby for use in multi-level metallization

• US 20040052930A1
• Filed: 09/16/2003
• Published: 03/18/2004
• Est. Priority Date: 04/27/2000
• Status: Active Grant

• Current Assignee: Novellus Systems Incorporated (Lam Research Corporation)
• Original Assignee: ASM NuTool, Inc. (ASM International NV)
• Inventors: Talieh, Homayoun, Basol, Bulent, Uzoh, Cyprian
• Granted Patent: US 6,974,769 B2
• Time in Patent Office: Days
• US Class Current: 427/58
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation

Abstract

Conductive structures in features of an insulator layer on a substrate are fabricated by a particular process. In this process, a layer of conductive material is applied over the insulator layer so that the layer of conductive material covers field regions adjacent the features and fills in the features themselves. A grain size differential between the conductive material which covers the field regions and the conductive material which fills in the features is then established by annealing the layer of conductive material. Excess conductive material is then removed to uncover the field regions and leave the conductive structures. The layer of conductive material is applied so as to define a first layer thickness over the field regions and a second layer thickness in and over the features. These thicknesses are dimensioned such that d₁≦0.5d₂, with d₁ being the first layer thickness and d₂ being the second layer thickness. Preferably, the first and second layer thicknesses are dimensioned such that d₁≦0.3d₂.

Claims

1. A process of fabricating conductive structures in features of an insulator layer on a substrate comprising:

applying a layer of conductive material over the insulator layer so that the layer of conductive material covers field regions adjacent said features and fills in said features,

establishing a grain size differential between the conductive material which covers said field regions and the conductive material which fills in said features by annealing said layer of conductive material, and

removing excess conductive material to uncover said field regions and leave said conductive structures.

2. The process according to claim 1, wherein said layer of conductive material is applied so as to define a first layer thickness over said field regions and a second layer thickness in and over said features.

3. The process according to claim 2, wherein said first layer thickness and said second layer thickness are dimensioned such that d₁≦

0.5d₂, with d₁ being said first layer thickness and d₂ being said second layer thickness.

4. The process according to claim 3, wherein said first and said second layer thicknesses are dimensioned such that d₁≦

0.3d₂.

5. The process according to claim 2, wherein applying the layer of conductive material over the insulator layer includes depositing the layer of conductive material over the insulator layer, and partially removing the layer of conductive material from over said field regions to establish a desired thickness differential between the first and second layer thicknesses.

6. The process according to claim 2, wherein applying the layer of conductive material over the insulator layer includes depositing a planarized layer of conductive material over the insulator layer to establish a desired thickness differential between the first and second layer thicknesses.

7. The process according to claim 5, wherein said first layer thickness and said second layer thickness are dimensioned such that d₁≦

0.5d₂, with d₁ being said first layer thickness and d₂ being said second layer thickness.

8. The process according to claim 7, wherein said first and said second layer thicknesses are dimensioned such that d₁≦

0.3d₂.

9. The process according to claim 6, wherein said first layer thickness and said second layer thickness are dimensioned such that d₁≦

0.5d₂, with d₁ being said first layer thickness and d₂ being said second layer thickness.

10. The process according to claim 9, wherein said first and said second layer thicknesses are dimensioned such that d₁≦

0.3d₂.

11. The process according to claim 1, wherein said conductive material is copper.

12. The process according to claim 1, wherein said conductive material is a copper alloy.

13. The process according to claim 1, wherein removing the excess conductive material is done by chemical mechanical polishing, chemical etching, electrochemical etching, or any combination of chemical mechanical polishing, chemical etching and electrochemical etching.

14. The process according to claim 1, wherein establishing said grain size differential also establishes a differential in chemical removal rates, physical removal rates, or both chemical and physical removal rates at which the excess conductive material can be removed from over said field regions and over said features.