Electronic device and method for fabricating the electronic device

• US 20040053435A1
• Filed: 06/23/2003
• Published: 03/18/2004
• Est. Priority Date: 06/24/2002
• Status: Active Grant

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Komobuchi, Hiroyoshi, Ikushima, Kimiya, Uchida, Mikiya
• Granted Patent: US 6,787,387 B2
• Time in Patent Office: Days
• US Class Current: 438/57
• CPC Class Codes: B81B 2201/0207 Bolometers
• CPC Class Codes: B81B 2203/0127 Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function
• CPC Class Codes: B81B 3/0072 For controlling internal stress or strain in moving or flexible elements, e.g. stress compensating layers
• CPC Class Codes: B81C 1/00047 Cavities
• CPC Class Codes: B81C 1/00801 Avoid alteration of functional structures by etching, e.g. using a passivation layer or an etch stop layer B81C1/00595, B81C1/00468 take precedence
• CPC Class Codes: B81C 2201/0109 Sacrificial layers not provided for in B81C2201/0107 - B81C2201/0108
• CPC Class Codes: B81C 2201/014 by depositing an etch stop layer, e.g. silicon nitride, silicon oxide, metal
• CPC Class Codes: G01F 1/6845 Micromachined devices
• CPC Class Codes: G01J 5/023 Particular leg structure or construction or shape; Nanotubes
• CPC Class Codes: G01J 5/024 Special manufacturing steps or sacrificial layers or layer structures
• CPC Class Codes: G01J 5/045 Sealings; Vacuum enclosures; Encapsulated packages; Wafer bonding structures; Getter arrangements getter arrangements per se H01L23/26 and H01L21/3221
• CPC Class Codes: G01J 5/10 using electric radiation detectors
• CPC Class Codes: G01J 5/20 using resistors, thermistors or semiconductors sensitive to radiation, e.g. photoconductive devices
• CPC Class Codes: G01J 5/34 using capacitors, e.g. pyroelectric capacitors

Abstract

A method for fabricating an electronic device includes the steps of: preparing a cavity defining sacrificial layer, at least the upper surface of which is covered with an etch stop layer; forming at least one first opening in the etch stop layer, thereby partially exposing the surface of the cavity defining sacrificial layer; etching the cavity defining sacrificial layer through the first opening, thereby defining a provisional cavity under the etch stop layer and a supporting portion that supports the etch stop layer thereon; and etching away a portion of the etch stop layer, thereby defining at least one second opening that reaches the provisional cavity through the etch stop layer and expanding the provisional cavity into a final cavity.

Claims

1. A method for fabricating an electronic device, the method comprising the steps of:

(a) preparing a cavity defining sacrificial layer, at least the upper surface of which is covered with an etch stop layer;

(b) forming at least one first opening in the etch stop layer, thereby partially exposing the surface of the cavity defining sacrificial layer;

(c) etching the cavity defining sacrificial layer through the first opening, thereby defining a provisional cavity under the etch stop layer and a supporting portion that supports the etch stop layer thereon; and

(d) etching away a portion of the etch stop layer, thereby defining at least one second opening that reaches the provisional cavity through the etch stop layer and expanding the provisional cavity into a final cavity.

2. The method of claim 1, wherein the step (d) includes the step of etching at least a part of the supporting portion, which is located under the second opening, through the second opening.

3. The method of claim 1, further comprising the step of forming a structure, including a patterned thin film, on the etch stop layer before the step (d) is performed.

4. The method of claim 3, wherein the step of forming the structure includes the step of forming the structure such that the patterned thin film does not overlap with the portion of the etch stop layer to be removed to define the second opening in the step (d).

5. The method of claim 1, wherein the step (a) comprises the steps of:

depositing a material film of the cavity defining sacrificial layer on a substrate; and

patterning the material film into the shape of the cavity defining sacrificial layer.

6. The method of claim 5, wherein the step of patterning the material film includes the step of patterning the material film into a cavity defining sacrificial layer that has a through hole extending from the upper surface thereof through the lower surface thereof.

7. The method of claim 5 or 6, wherein the step (c) includes the step of defining the supporting portion in a region in which the cavity defining sacrificial layer is not present.

8. The method of claim 7, wherein the step (c) includes the step of making a portion of the etch stop layer function as the supporting portion.

9. The method of claim 5, wherein the step (c) includes the step of leaving a portion of the cavity defining sacrificial layer as the supporting portion.

10. The method of claim 2, wherein the step (c) includes the step of selectively removing the cavity defining sacrificial layer by a wet etching technique, and

wherein the step (d) includes the step of removing the supporting portion at least partially by a dry etching technique.

11. The method of claim 1, wherein the step (a) includes the step of depositing the etch stop layer on the cavity defining sacrificial layer.

12. The method of claim 1, wherein the step (a) includes the step of preparing an SOI substrate that includes a silicon dioxide layer functioning as the etch stop layer and a single crystalline silicon substrate including a portion functioning as the cavity defining sacrificial layer.

13. The method of claim 1, further comprising the steps of:

defining a mask, having a pattern that will define the second opening and that exposes the inside of the first opening, on the etch stop layer between the steps (b) and (c); and

removing the mask after the step (d) has been performed.

14. The method of claim 1, further comprising, between the steps (c) and (e), the steps of:

depositing a thin film on the etch stop layer to close up the first opening of the etch stop layer;

forming a film for a sensor on the thin film; and

patterning the film for the sensor.

15. The method of claim 14, wherein the step of depositing the thin film includes the step of depositing the thin film by a chemical vapor deposition process.

16. The method of claim 15, further comprising the step of forming a heat-absorbing insulating film on the thin film.

17. The method of claim 16, further comprising the step of forming a passivation film on the heat-absorbing insulating film.

18. The method of claim 1, wherein the step (a) includes the step of locally oxidizing the surface of a single crystalline silicon substrate to define a silicon dioxide region on a selected area on the surface of the silicon substrate, at least a portion of the silicon dioxide region being used as the cavity defining sacrificial layer.

19. The method of claim 18, further comprising the step of using the silicon dioxide region as an isolation film.

20. The method of claim 1, wherein the step (a) includes the step of using a surface portion of a semiconductor substrate as the cavity defining sacrificial layer.

21. The method of claim 1, wherein the step (c) includes the steps of:

forming a recess, extending from the first opening into the cavity defining sacrificial layer, by a dry etching technique; and

expanding the recess by an isotropic etching technique.

22. The method of claim 1, wherein the step (c) includes the step of defining the supporting portion only around the provisional cavity.

23. The method of claim 1, wherein the step (c) includes the step of defining the supporting portion only inside of the provisional cavity.

24. The method of claim 21, wherein the step (c) includes the step of defining three to ten columns, each having a transversal sectional area of at least about 10 μ

m², as the supporting portion where the final cavity has an overall transversal sectional area of about 1,000 μ

m² or more.

25. The method of claim 14, wherein the step (a) includes the step of depositing a nitride layer as the etch stop layer, and

wherein the step of depositing the thin film includes the step of depositing a silicon dioxide film.

26. The method of claim 4, further comprising the step of forming a cap member that encapsulates the structure including the patterned thin film.

27. An electronic device comprising:

a substrate with at least one cavity;

a thin film structure, which defines the upper surface of the cavity; and

a patterned thin film that is supported by the thin film structure,

wherein the thin film structure includes at least one hole, which is not overlapped by the patterned thin film and which reaches the cavity.

28. The device of claim 27, wherein a convex portion is provided inside of the cavity and right under the hole so as to protrude toward the thin film structure.

29. The device of claim 27, wherein a concave portion is provided inside of the cavity and right under the hole so as to protrude away from the thin film structure.

30. The device of claim 27, wherein the patterned thin film is a bolometer, and

wherein the electronic device functions as an infrared sensor.