Semiconductor device and manufacturing method thereof

• US 20040053502A1
• Filed: 11/14/2002
• Published: 03/18/2004
• Est. Priority Date: 09/17/2002
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Iguchi, Tadashi, Sonoda, Masahisa, Sakagami, Eiji, Tsunoda, Hiroaki
• Granted Patent: US 6,984,858 B2
• Time in Patent Office: Days
• US Class Current: 438/694
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Abstract

In a semiconductor device including a plurality of element regions and an element isolation region based on STI (shallow trench isolation) which electrically isolates the element regions from each other, each of the element regions includes; a channel region; source/drain regions formed to sandwich the channel region in a horizontal direction; a gate insulation film which is formed on the channel region and in which an angle of a bird'"'"'s beak is 1 degree or smaller, the bird'"'"'s beak being formed from a side of the element isolation region on a surface opposite a surface facing the channel region in a horizontal direction substantially perpendicular to the direction in which the source/drain region sandwich the channel region; and a gate electrode layer formed on the gate insulation film.

Claims

1. A semiconductor device comprising a plurality of element regions and an element isolation region based on STI which electrically isolates the element regions from each other, each of the element regions comprising:

a channel region;

source/drain regions formed to sandwich the channel region in a horizontal direction;

a gate insulation film which is formed on the channel region and in which an angle of a bird'"'"'s beak is 1 degree or smaller, the bird'"'"'s beak being formed from a side of the element isolation region on a surface opposite a surface in contact with the channel region in a horizontal direction substantially perpendicular to the direction in which the source/drain regions sandwich the channel region; and

a gate electrode layer formed on the gate insulation film.

2. A semiconductor device as set forth in claim 1, wherein the gate electrode layer is in an electrically floating state.

3. A semiconductor device as set forth in claim 1, wherein the gate electrode layer is a polycrystalline silicon film.

4. A semiconductor device as set forth in claim 1, wherein a length of the gate insulation film is 200 nm or shorter in the horizontal direction substantially perpendicular to the direction in which the source/drain regions sandwich the channel region.

5. A semiconductor device as set forth in claim 1, wherein, in the gate insulation film, a depth of the bird'"'"'s beak from the side of the element isolation region is 10% or smaller relative to a length of the gate insulation film in the horizontal direction substantially perpendicular to the direction in which the source/drain regions sandwich the channel region.

6. A semiconductor device comprising a plurality of element regions and an element isolation region based on STI which electrically isolates the element regions from each other, each of the element regions comprising:

a channel region;

source/drain regions formed to sandwich the channel region in a horizontal direction;

a gate insulation film having a side surface and formed on the channel region with this side surface being continuous with a side surface of the channel region on a side of the element isolation region; and

a gate electrode layer having a side surface and formed on the gate insulation film with this side surface being continuous with the side surface of the gate insulation film on the side of the element isolation region.

7. A semiconductor device as set forth in claim 6, wherein the gate electrode layer is in an electrically floating state.

8. A semiconductor device as set forth in claim 6, wherein the gate electrode layer is a polycrystalline silicon film.

9. A semiconductor device as set forth in claim 6, wherein a length of the gate insulation film is 200 nm or shorter in the horizontal direction substantially perpendicular to the direction in which the source/drain regions sandwich the channel region.

10. A semiconductor device manufacturing method, comprising:

forming a gate insulation film on a substrate;

forming a gate electrode layer on the gate insulation film;

forming a trench structured to pass through the gate electrode layer and the gate insulation film and to dig into the substrate; and

burying an insulation film in the trench to be in direct contact with a side surface of the gate electrode layer in the trench and a side surface of the substrate in the trench.

11. A semiconductor device manufacturing method asset forth in claim 10, wherein, in the forming the gate electrode layer on the gate insulation film, a polycrystalline silicon layer is formed as the gate electrode layer.

12. A semiconductor device as set forth in claim 10, wherein, in the forming the trench structured to pass through the gate electrode layer and the gate insulation film and to dig into the substrate, a plurality of trenches substantially parallel to each other are formed, and the trenches are formed to make an internal dimension between the trenches parallel and adjacent to each other be 200 nm or smaller.