High-electron mobility transistor with zinc oxide

• US 20040056273A1
• Filed: 06/24/2003
• Published: 03/25/2004
• Est. Priority Date: 06/24/2002
• Status: Active Grant

• Current Assignee: Catherine D. Nause
• Original Assignee: Cermet, Inc.
• Inventors: Nause, Jeff, Ganesan, Shanthi
• Granted Patent: US 7,105,868 B2
• Time in Patent Office: Days
• US Class Current: 257/194
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/22 including, apart from doping materials or other impurities, only AIIBVI compounds
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Abstract

A zinc oxide (ZnO) field effect transistor exhibits large input amplitude by using a gate insulating film. A channel layer and a gate insulating film are sequentially n laminated on a substrate. A gate electrode is formed on the gate insulating film. A source electrode and a drain electrode are disposed at the both sides of the gate electrode and are electrically connected to the channel layer via openings. The channel layer is formed from n-type ZnO. The gate insulating film is made from aluminum nitride/aluminum gallium nitride (AlN/AlGaN) or magnesium zinc oxide (MgZnO), which exhibits excellent insulation characteristics, thus increasing the Schottky barrier and achieving large input amplitude. If the FET is operated in the enhancement mode, it is operable in a manner similar to a silicon metal oxide semiconductor field effect transistor (Si-MOS-type FET), resulting in the formation of an inversion layer.

Claims

1. A high electron mobility transistor (HEMT) comprising:

a channel layer being composed of a II-VI compound semiconductor zinc oxide;

a gate electrode disposed on said channel layer; and

a gate insulating film disposed between said gate electrode and said channel layer and composed of at least one of a Group-III nitride compound semiconductor and a magnesium zinc oxide (MgZnO) quantum well structure.

2. A HEMT according to claim 1 wherein said gate insulating film is composed of at least one of an epitaxially grown Group-III nitride compound semiconductor and a MgZnO quantum well structure.

3. A HEMT according to claim 2 wherein said channel layer is composed of an epitaxially grown Group-II-VI zinc oxide compound semiconductor.

4. A HEMT according to claim 1 wherein said gate insulating film is composed of a Group-III compound semiconductor expressed by a chemical formula Al_x Ga_1-x N (0.3≦

x≦

1) or Mg_x Zn_1-x O (0.1<

x.<

0.4).

5. A HEMT according to claim 1 wherein said substrate comprises at least one of zinc oxide (ZnO), silicon carbide (SiC), sapphire (Al₂O₃), and silicon (Si) and has a bulk resistivity higher than 10⁵ ohm-centimeter (Ω

-cm).

6. A HEMT according to claim 1 wherein the thickness of said gate insulating film ranges from 0.30 nanometer (nm) to 50 nm.

7. A HEMT according to claim 1 employs piezoelectric doping that produces a two-dimensional electron gas (2DEG) near the interface avoiding the usage of a conventional doping method.

8. A HEMT according to claim 1 wherein said gate contact is a rectifying contact selected from the group consisting of titanium (Ti), platinum (Pt), silver (Ag), gold (Au), chromium (Cr), alloys of titanium (Ti) and tungsten (W), and platinum silicide (PtSi).

9. A HEMT according to claim 1 wherein said source and drain contacts comprise an alloy of titanium (Ti), silicon (Si), aluminum (Al) and nickel (Ni).

10. A HEMT according to claim 1 and further comprising a passivation layer on said gate and said rectifying contacts and on said heterojunction.

11. A HEMT according to claim 1 wherein said gate electrode has side walls on the lateral surfaces thereof.

12. A HEMT according to claim 1 wherein the contact area of said gate electrode with said gate-insulating film is decreased due to the presence of said sidewalls.

13. A HEMT according to claim 1 wherein the a channel layer is composed of ZnO and is grown by MOCVD.

14. A HEMT according to claim 1 wherein gate insulating film is grown by metal organic chemical vapor deposition (MOCVD) and sequentially laminated on a ZnO channel, and the ZnO channel in turn is laminated onto a ZnO substrate.

15. A HEMT according to claim 14 wherein the ZnO substrate is a c-surface substrate.

16. A HEMT according to claim 1 wherein, after the gate-insulating-film forming layer is formed on the channel layer, the dummy gate is formed, and the side walls are made on the lateral surfaces of the dummy gate, and the gate-insulating-film-forming layer is then selectively removed by using the dummy gate and the sidewalls as a mask, thereby forming a gate insulating film.

17. A method comprising:

defining a channel layer composed of a II-VI compound semiconductor zinc oxide;

forming a gate electrode disposed on said channel layer; and

forming a gate insulating film disposed between said gate electrode and said channel layer and composed of at least one of a Group-III nitride compound semiconductor and a magnesium zinc oxide (MgZnO) quantum well structure.

18. A method according to claim 17 wherein the gate insulating film is formed by metal organic chemical vapor deposition (MOCVD).

19. A method according to claim 17 wherein the ZnO substrate is a c-surface substrate.

20. A method according to claim 17 wherein, after the gate-insulating-film forming layer is formed on the channel layer, a dummy gate is formed, and side walls are made on the lateral surfaces of the dummy gate, and the gate-insulating-film-forming layer is then selectively removed by using the dummy gate and the sidewalls as a mask, thereby forming the gate insulating film.