Semiconductor device, semiconductor package member, and semiconductor device manufacturing method

• US 20040056341A1
• Filed: 09/17/2003
• Published: 03/25/2004
• Est. Priority Date: 09/19/2002
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Endo, Mitsuyoshi, Takubo, Chiaki, Matsuo, Mie
• Granted Patent: US 7,095,112 B2
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/83102 using surface energy, e.g. capillary forces
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19011 : including integrated passive components
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Provided a semiconductor device including: a wiring board; a semiconductor chip having a pad electrically connected to a wiring on the wiring board; a second semiconductor chip provided on the wiring board at a position facing a side of the semiconductor chip, having passive elements integrated therein, and having pads for external connection to which both ends of the passive elements are connected respectively and at least one of which is electrically connected to the wiring on the wiring board electrically connected to the pad of the semiconductor chip.

Claims

1. A semiconductor device, comprising:

a wiring board;

a semiconductor chip provided on said wiring board and having a pad electrically connected to a wiring on said wiring board; and

a second semiconductor chip provided on said wiring board at a position facing a side of said semiconductor chip, having passive elements integrated therein, and having pads for external connection to which both ends of the passive elements are connected respectively and at least one of which is electrically connected to the wiring on said wiring board electrically connected to the pad of said semiconductor chip.

2. A semiconductor device as set forth in claim 1, wherein the passive elements integrated in said second semiconductor chip are elements of one kind, or two kinds or more selected from a group of a capacitor, a resistor, and an inductor.

3. A semiconductor device as set forth in claim 1, wherein said semiconductor chip is flipchip-connected to said wiring board so as to electrically connect the pad to the wiring on said wiring board.

4. A semiconductor device as set forth in claim 1, wherein said semiconductor chip has bonding wire connection to the wiring of said wiring board so as to electrically connect the pad to the wiring on said wiring board.

5. A semiconductor device as set forth in claim 1, wherein said second semiconductor chip is flipchip-connected to said wiring board so as to electrically connect the pads for external connection to the wiring on said wiring board.

6. A semiconductor device as set forth in claim 1, wherein said second semiconductor chip has bonding wire connection to the wiring of said wiring board so as to electrically connect the pads for external connection to the wiring on said wiring board.

7. A semiconductor device as set forth in claim 1, wherein said semiconductor chip and said second semiconductor chip are both 60 μ

m or less in thickness.

8. A semiconductor device as set forth in claim 5, wherein said second semiconductor chip has, besides the pads for external connection used for the flipchip connection to said wiring board, a pad for external connection not contributing to the flipchip connection to said wiring board.

9. A semiconductor device, comprising:

a plurality of semiconductor device portion units arranged in a lamination direction and each including;

a wiring board;

a semiconductor chip provided on said wiring board and having a pad electrically connected to a wiring on said wiring board; and

a second semiconductor chip provided on said wiring board at a position facing a side of said semiconductor chip, having passive elements integrated therein, and having pads for external connection to which both ends of the passive elements are connected respectively and at least one of which is electrically connected to the wiring on said wiring board electrically connected to the pad of said semiconductor chip; and

a vertical wiring portion passing through said wiring boards of said plural semiconductor device portion units and electrically connecting said wiring boards to one another.

10. A semiconductor device as set forth in claim 9, wherein the passive elements integrated in said second semiconductor chips of the respective plural semiconductor device portion units are elements of one kind, or two kinds or more selected from a group of a capacitor, a resistor, and an inductor.

11. A semiconductor package member, comprising:

a wiring board on which a semiconductor chip is mountable; and

an auxiliary semiconductor chip provided on said wiring board at a position facing a side of said semiconductor chip to be mounted, having passive elements integrated therein, and having pads for external connection to which both ends of the passive elements are connected respectively and at least one of which is electrically connected to a wiring on said wiring board.

12. A semiconductor package member as set forth in claim 11, wherein the passive elements integrated in said auxiliary semiconductor chips are elements of one kind, or two kinds or more selected from a group of a capacitor, a resistor, and an inductor.

13. A semiconductor device manufacturing method, comprising:

mounting on a wiring board a semiconductor chip having a pad so as to electrically connect the pad and a wiring on the wiring board; and

mounting a second semiconductor chip having passive elements integrated therein and having pads for external connection to which both ends of the passive elements are connected respectively, on the wiring board at a position facing a side of the semiconductor chip so as to electrically connect at least one of the pads for external connection to the wiring on the wiring board electrically connected to the pad of the semiconductor chip.