Stacked die module and techniques for forming a stacked die module

• US 20040056342A1
• Filed: 09/25/2003
• Published: 03/25/2004
• Est. Priority Date: 05/08/2002
• Status: Active Grant

• Current Assignee: Chad A. Cobbley, Timothy L. Jackson
• Original Assignee: Chad A. Cobbley, Timothy L. Jackson
• Inventors: Cobbley, Chad A., Jackson, Timothy L.
• Granted Patent: US 7,755,204 B2
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06579 TAB carriers; beam leads
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: Y10T 156/10 : Methods of surface bonding and/or assembly therefor

Abstract

A technique for forming die stacks. Specifically, a stacking tip is provided to facilitate the stacking of die in a desired configuration. A first die is picked up by the stacking tip. The first die is coated with an adhesive on the underside of the die. The first die is brought in contact with a second die via the stacking tip. The second die is coupled to the first die via the adhesive on the underside of the first die. The second die is coated with an adhesive coating on the underside of the die. The second die is then brought in contact with a third die via the stacking tip. The third die is coupled to the second die via the adhesive on the underside of the second die, and so forth. Die stacks are formed without being coupled to a substrate. The die stacks may be functionally and/or environmentally tested before attaching the die stack to a substrate.

Claims

1. A method of stacking semiconductor die comprising the acts of:

a) picking up a first die having a topside and an underside with a die picking tool;

b) applying adhesive to the underside of the first die, thereby providing an adhesively coated underside of the first die; and

c) without releasing the first die from the die picking tool, picking up a second die having a topside and an underside by placing the adhesively coated underside of the first die against the topside of the second die, thereby forming a die stack.

2. The method of stacking semiconductor die, as set forth in claim 1, wherein the first die is thicker than the second die.

3. The method of stacking semiconductor die, as set forth in claim 1, wherein the acts are performed in the recited order.

4. The method of stacking semiconductor die, as set forth in claim 1, wherein act (b) is performed before act (a).

5. The method of stacking semiconductor die, as set forth in claim 1, comprising the act of applying adhesive to the underside of the second die, thereby providing an adhesively coated underside of the second die.

6. The method of stacking semiconductor die, as set forth in claim 5, comprising the act of without releasing the first die from the picking tool, picking up a third die having a topside and an underside by placing the adhesively coated underside of the second die against the topside of the third die.

7. The method of stacking semiconductor die, as set forth in claim 1, comprising the act of placing the die stack onto a temporary holding surface.

8. The method of stacking semiconductor die, as set forth in claim 7, wherein the temporary holding surface comprises a film frame.

9. The method of stacking semiconductor die, as set forth in claim 7, wherein the temporary holding surface comprises a gel pack.

10. The method of stacking semiconductor die, as set forth in claim 7, wherein the temporary holding surface comprises a wafer.

11. The method of stacking semiconductor die, as set forth in claim 1, comprising the act of attaching the die stack to a substrate.

12. A method of stacking semiconductor die comprising the acts of:

(a) forming a stack of at least two semiconductor die; and

(b) placing the stack onto a temporary holding surface.

13. The method of stacking semiconductor die, as set forth in claim 12, where act (a) comprises the acts of:

a) picking up a first die having a topside and an underside with a die picking tool;

b) applying adhesive to the underside of the first die, thereby providing an adhesively coated underside of the first die; and

c) without releasing the first die from the die picking tool, picking up a second die having a topside and an underside by placing the adhesively coated underside of the first die against the topside of the second die, thereby forming a die stack.

14. The method of stacking semiconductor die, as set forth in claim 13, wherein the first die is thicker than the second die.

15. The method of stacking semiconductor die, as set forth in claim 13, wherein the acts are performed in the recited order.

16. The method of stacking semiconductor die, as set forth in claim 13, wherein act (b) is performed before act (a).

17. The method of stacking semiconductor die, as set forth in claim 13, comprising the act of applying adhesive to the underside of the second die, thereby providing an adhesively coated underside of the second die.

18. The method of stacking semiconductor die, as set forth in claim 17, comprising the act of without releasing the first die from the picking tool, picking up a third die having a topside and an underside by placing the adhesively coated underside of the second die against the topside of the third die.

19. The method of stacking semiconductor die, as set forth in claim 12, wherein act (a) comprises the act of forming a stack of at least three semiconductor die.

20. The method of stacking semiconductor die, as set forth in claim 12, wherein act (b) comprises the act of placing the stack onto a film frame.

21. The method of stacking semiconductor die, as set forth in claim 12, wherein act (b) comprises the act of placing the stack onto a gel pack.

22. The method of stacking semiconductor die, as set forth in claim 12, wherein act (b) comprises the act of placing the stack onto a wafer.

23. The method of stacking semiconductor die, as set forth in claim 12, comprising the act of attaching the die stack to a substrate.

24. A method of testing semiconductor die comprising the acts of:

(a) forming a stack of at least two semiconductor die; and

(b) after the stack is formed, testing the semiconductor die in the stack prior to attaching the semiconductor die to a packaging substrate.

25. The method of testing semiconductor die, as set forth in claim 24, where act (a) comprises the acts of:

a) picking up a first die having a topside and an underside with a die picking tool;

b) applying adhesive to the underside of the first die, thereby providing an adhesively coated underside of the first die; and

c) without releasing the first die from the die picking tool, picking up a second die having a topside and an underside by placing the adhesively coated underside of the first die against the topside of the second die, thereby forming a die stack.

26. The method of testing semiconductor die, as set forth in claim 25, wherein the first die is thicker than the second die.

27. The method of testing semiconductor die, as set forth in claim 25, wherein the acts are performed in the recited order.

28. The method of testing semiconductor die, as set forth in claim 25, wherein act (b) is performed before act (a).

29. The method of testing semiconductor die, as set forth in claim 25, comprising the act of applying adhesive to the underside of the second die, thereby providing an adhesively coated underside of the second die.

30. The method of testing semiconductor die, as set forth in claim 29, comprising the act of without releasing the first die from the picking tool, picking up a third die having a topside and an underside by placing the adhesively coated underside of the second die against the topside of the third die.

31. The method of testing semiconductor die, as set forth in claim 24, wherein act (a) comprises the act of forming a stack of at least three semiconductor die.

32. The method of testing semiconductor die, as set forth in claim 24, wherein act (b) comprises the act of after the stack is formed, functionally testing the semiconductor die in the stack prior to attaching the semiconductor die to a packaging substrate.

33. The method of testing semiconductor die, as set forth in claim 24, wherein act (b) comprises the act of after the stack is formed, environmental testing the semiconductor die in the stack prior to attaching the semiconductor die to a packaging substrate.

34. The method of testing semiconductor die, as set forth in claim 24, comprising the act of coupling the tested stack to a packaging substrate.

35. An integrated circuit comprising:

a stack comprising at least two semiconductor die, each of the semiconductor die being coupled together by a first adhesive, the first adhesive being curable at a first temperature; and

a substrate coupled to one of the at least two semiconductor die by a second adhesive, the second adhesive being curable at a second temperature lower than the first temperature.

36. The integrated circuit, as set forth in claim 35, wherein one of the at least two semiconductor die is thicker than a second of the at least two semiconductor die.

37. The integrated circuit, as set forth in claim 35, wherein the topside surface area of one of the at least two semiconductor die is less than the topside surface area of a second of the at least two semiconductor die.

38. The integrated circuit, as set forth in claim 35, wherein the stack of at least two semiconductor die is configured such that the stack comprises a shingle stack.

39. The integrated circuit, as set forth in claim 35, wherein at least one of the at least two semiconductor die comprises a memory die.

40. A system comprising:

a processor; and

an integrated circuit coupled to the processor and comprising;

a stack comprising at least two semiconductor die, each of the semiconductor die being coupled together by a first adhesive, the first adhesive being curable at a first temperature; and

a substrate coupled to one of the at least two semiconductor die by a second adhesive, the second adhesive being curable at a second temperature lower than the first temperature.

41. The system, as set forth in claim 40, wherein one of the at least two semiconductor die is thicker than a second of the at least two semiconductor die.

42. The system, as set forth in claim 40, wherein the topside surface area of one of the at least two semiconductor die is less than the topside surface area of a second of the at least two semiconductor die.

43. The system, as set forth in claim 40, wherein the stack of at least two semiconductor die is configured such that the stack comprises a shingle stack.

44. The system, as set forth in claim 40, wherein at least one of the at least two semiconductor die comprises a memory die.

45. An integrated circuit comprising a stack of at least two semiconductor die, each of the die being coupled to an adjacent die in the stack by a respective layer of adhesive prior to the stack being coupled to a packaging substrate.

46. The integrated circuit, as set forth in claim 45, wherein one of the at least two semiconductor die is thicker than a second of the at least two semiconductor die.

47. The integrated circuit, as set forth in claim 45, wherein the topside surface area of one of the at least two semiconductor die is less than the topside surface area of a second of the at least two semiconductor die.

48. The integrated circuit, as set forth in claim 45, wherein the stack of at least two semiconductor die is configured such that the stack comprises a shingle stack.

49. The integrated circuit, as set forth in claim 45, wherein at least one of the at least two semiconductor die comprises a memory die.

50. A tape reel having a plurality of semiconductor die stacks thereon.

51. The tape reel, as set forth in claim 50, wherein each of the die stacks comprises at least two semiconductor die, each of the semiconductor die being coupled together by an adhesive.

52. The tape reel, as set forth in claim 51, wherein one of the at least two semiconductor die is thicker than a second of the at least two semiconductor die.

53. The tape reel, as set forth in claim 51, wherein the topside surface area of one of the at least two semiconductor die is less than the topside surface area of a second of the at least two semiconductor die.

54. The tape reel, as set forth in claim 51, wherein the stack of at least two semiconductor die is configured such that the stack comprises a shingle stack.

55. The tape reel, as set forth in claim 51, wherein at least one of the at least two semiconductor die comprises a memory die.

56. A method of forming a semiconductor package comprising the acts of:

picking a die stack from a temporary holding surface; and

placing the die stack on a substrate.

57. The method of forming a semiconductor package, as set forth in claim 56, comprising the act of before the act of picking a die stack, curing the die stack.

58. The method of forming a semiconductor package, as set forth in claim 56, comprising the act of before the act of picking a die stack, testing the die stack.

59. The method of forming a semiconductor package, as set forth in claim 56, wherein the act of picking the die stack from a temporary holding surface comprises the act of picking the die stack from a tape reel.

60. The method of forming a semiconductor package, as set forth in claim 56, wherein the act of picking the die stack from a temporary holding surface comprises the act of picking the die stack from a gel pack.

61. The method of forming a semiconductor package, as set forth in claim 56, wherein the act of picking the die stack from a temporary holding surface comprises the act of picking the die stack from a tray.

62. The method of forming a semiconductor package, as set forth in claim 56, wherein the act of picking the die stack from a temporary holding surface comprises the act of picking the die stack from a wafer.