Current-controlled CMOS wideband data amplifier circuits
First Claim
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1. An amplifier stage comprising:
- a current source;
a first differential transistor having a source, gate, and drain, wherein the source of the first differential transistor is coupled to the current source;
a second differential transistor having a source, gate, and drain, wherein the source of the second differential transistor is coupled to the current source;
a first series peaking inductor having positive and negative ends, wherein the negative end coupled of the first series peaking inductor is coupled to the gate of the first differential transistor;
a second series peaking inductor having positive and negative ends, wherein the negative end of the second series peaking inductor is coupled to the gate of the second differential transistor;
a first output resistor having positive and negative ends, wherein the negative end of the first output resistor is coupled to the drain the first differential transistor;
a second output resistor having positive and negative ends, wherein the negative end of the second output resistor is coupled to the drain of the second differential transistor;
a first shunt peaking inductor having positive and negative ends, wherein the negative end of the first shunt peaking inductor is coupled to the positive end of the first output resistor; and
a second shunt peaking inductor having positive and negative ends, wherein the negative end of the second shunt peaking inductor is coupled to the positive end of the second output resistor.
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Abstract
Expansion of the bandwidth of a wideband CMOS data amplifier is accomplished using various combinations of shunt peaking, series peaking, and miller capacitance cancellation. These various combinations are employed in any of the amplifier input stage, in intermediate stages, or in the last stage.
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Citations
29 Claims
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1. An amplifier stage comprising:
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a current source;
a first differential transistor having a source, gate, and drain, wherein the source of the first differential transistor is coupled to the current source;
a second differential transistor having a source, gate, and drain, wherein the source of the second differential transistor is coupled to the current source;
a first series peaking inductor having positive and negative ends, wherein the negative end coupled of the first series peaking inductor is coupled to the gate of the first differential transistor;
a second series peaking inductor having positive and negative ends, wherein the negative end of the second series peaking inductor is coupled to the gate of the second differential transistor;
a first output resistor having positive and negative ends, wherein the negative end of the first output resistor is coupled to the drain the first differential transistor;
a second output resistor having positive and negative ends, wherein the negative end of the second output resistor is coupled to the drain of the second differential transistor;
a first shunt peaking inductor having positive and negative ends, wherein the negative end of the first shunt peaking inductor is coupled to the positive end of the first output resistor; and
a second shunt peaking inductor having positive and negative ends, wherein the negative end of the second shunt peaking inductor is coupled to the positive end of the second output resistor. - View Dependent Claims (3, 4, 5)
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2. An amplifier stage as in claim, further comprising:
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a first miller capacitance cancellation capacitor having positive and negative ends, wherein the positive end of the first miller capacitance cancellation capacitor is coupled to the drain of the second differential transistor, and wherein the negative end of the first miller capacitance cancellation capacitor is coupled to the gate of the first differential transistor; and
a second miller capacitance cancellation capacitor having positive and negative ends, wherein the positive end of the second miller capacitance cancellation capacitor is coupled to the drain of the first differential transistor, and wherein the negative end of the second miller capacitance cancellation capacitor is coupled to the gate of the second differential transistor.
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6. An amplifier stage comprising:
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a current source;
a first differential transistor having a source, gate, and drain, wherein the source of the first differential transistor is coupled to the current source;
a second differential transistor having a source, gate, and drain, wherein the source of the second differential transistor is coupled to the current source;
a first series peaking inductor having positive and negative ends, wherein the negative end coupled of the first series peaking inductor is coupled to the gate of the first differential transistor;
a second series peaking inductor having positive and negative ends, wherein the negative end of the second series peaking inductor is coupled to the gate of the second differential transistor;
a first shunt peaking inductor having positive and negative ends, wherein the negative end of the first shunt peaking inductor is coupled to the drain the first differential transistor;
a second shunt peaking inductor having positive and negative ends, wherein the negative end of the second shunt peaking inductor is coupled to the drain of the second differential transistor;
a first output resistor having positive and negative ends, wherein the negative end of the first output resistor is coupled to the positive end of the first shunt peaking inductor; and
a second output resistor having positive and negative ends, wherein the negative end of the second output resistor is coupled to the positive end of the first shunt peaking inductor. - View Dependent Claims (7, 8, 9, 10)
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11. A multi-stage differential amplifier comprising:
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a first amplifier stage having a positive signal input, a negative signal input, a positive signal output, and a negative signal output; and
a last amplifier stage having a positive signal input, a negative signal input, a positive signal output, and a negative signal output;
wherein the positive signal output of the first amplifier stage is coupled to the positive signal input of the last amplifier stage, and wherein the negative signal output of the first amplifier stage is coupled to the negative signal input of the last amplifier stage;
wherein one of the first amplifier stage and last amplifier stage includes a first pair of series peaking inductors; and
wherein one of the first amplifier stage and last amplifier stage includes a first pair of shunt peaking inductors. - View Dependent Claims (12, 13, 14, 15)
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16. A multi-stage differential amplifier comprising:
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a first amplifier stage having a positive signal input, a negative signal input, a positive signal output, and a negative signal output;
an intermediate amplifier stage having a positive signal input, a negative signal input, a positive signal output, and a negative signal output; and
a last amplifier stage having a positive signal input, a negative signal input, a positive signal output, and a negative signal output;
wherein the positive signal output of the first amplifier stage is coupled to the positive signal input of the intermediate amplifier stage, and wherein the negative signal output of the first amplifier stage is coupled to the negative signal input of the intermediate amplifier stage;
wherein the positive signal output of the intermediate amplifier stage is coupled to the positive signal input of the last amplifier stage, and wherein the negative signal output of the intermediate amplifier stage is coupled to the negative signal input of the last amplifier stage;
wherein one of the first amplifier stage, intermediate amplifier stage, and last amplifier stage includes a first pair of series peaking inductors; and
wherein one of the first amplifier stage, intermediate amplifier stage, and last amplifier stage includes a first pair shunt peaking inductors. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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23. A multi-stage differential amplifier comprising:
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a first amplifier stage having a positive signal input, a negative signal input, a positive signal output, and a negative signal output;
a plurality of intermediate amplifier stages, the plurality having a positive signal input, a negative signal input, a positive signal output, and a negative signal output; and
a last amplifier stage having a positive signal input, a negative signal input, a positive signal output, and a negative signal output;
wherein the positive signal output of the first amplifier stage is coupled to the positive signal input of the plurality of intermediate amplifier stages, and wherein the negative signal output of the first amplifier stage is coupled to the negative signal input of the plurality of intermediate amplifier stages;
wherein the positive signal output of the plurality of intermediate amplifier stages is coupled to the positive signal input of the last amplifier stage, and wherein the negative signal output of the plurality of intermediate amplifier stages is coupled to the negative signal input of the last amplifier stage;
wherein one of the first amplifier stage, plurality of intermediate stages, and last amplifier stage includes a first pair of series peaking inductors; and
wherein one of the first amplifier stage, plurality of intermediate amplifier stages, and last amplifier stage includes a first pair of shunt peaking inductors. - View Dependent Claims (24, 25, 26, 27, 28, 29)
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Specification