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Method of controlling an electronic non-volatile memory and associated device

  • US 20040057265A1
  • Filed: 07/09/2003
  • Published: 03/25/2004
  • Est. Priority Date: 07/11/2002
  • Status: Active Grant
First Claim
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1. Method of controlling a cell of an EEPROM memory (1) having a floating gate transistor (Mlec), the method comprising at least a step of setting a state of the cell (1), characterized in that:

  • the state setting step comprises applying simultaneously voltage pulses of opposite polarities respectively to the drain (DF, DS) and to the control gate (CG) of the floating gate transistor (Mlec);

    the pulses comprise;

    a first portion (11) having a slope greater than K*8 MegaVolts/s;

    a second portion (12) having a slope comprised between K*1 KiloVolts/s and K*1 MegaVolts/s;

    with K=1 when the pulse has a positive polarity, K=−

    1 when the pulse has a negative polarity.

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