FERROELECTRIC TRANSISTOR FOR STORING TWO DATA BITS

• US 20040057274A1
• Filed: 09/19/2002
• Published: 03/25/2004
• Est. Priority Date: 09/19/2002
• Status: Active Grant

• Current Assignee: COVA Technologies Incorporated
• Original Assignee: COVA Technologies Incorporated
• Inventors: Dimmler, Klaus, Gnadinger, Alfred P.
• Granted Patent: US 6,714,435 B1
• Time in Patent Office: Days
• US Class Current: 365/145
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 11/5657 using ferroelectric storage elements
• CPC Class Codes: H01L 29/78391 the gate comprising a layer which is used for its ferroelectric properties
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

Abstract

A method of storing and accessing two data bits in a single ferroelectric FET includes selectively polarizing two distinct ferroelectric regions in the same gate dielectric layer separated by a non-ferroelectric dielectric region. A first ferroelectric region is sandwiched between the substrate and the gate terminal in the region of the source and is polarized in one of two states to form a first data bit within the FET. A second ferroelectric region is sandwiched between the substrate and the gate terminal in the region of the drain and is polarized in one of two states to form a second data bit within the FET. Detection of the first data bit is accomplished by selectively applying a read bias to the FET terminals, a first current resulting when a first state is stored and a second current resulting when a second state is stored. The polarization of the second data bit is accomplished by reversing the source and drain voltages.

Claims

1. A ferroelectric field effect transistor (FET) exhibiting hysteresis, comprising:

a semiconductor substrate of a first conductivity type;

a source, said source comprising a region of said semiconductor substrate doped to have a conductivity opposite that of said semiconductor substrate;

a drain, spaced from said source, said drain comprising a portion of said semiconductor substrate doped to have a conductivity opposite of said substrate;

a channel being formed in the space between said source and said drain;

a gate dielectric layer comprising a first ferroelectric region overlaying the channel in the vicinity of the source, a second ferroelectric region overlaying the channel in the vicinity of the drain, and a non-ferroelectric dielectric overlaying the channel between the first and second ferroelectric region; and

a conductive electrode layer overlaying said gate dielectric layer.

2. The FET of claim 1 wherein first and second ferroelectric regions are formed utilizing sidewall deposition processing techniques.

3. The FET of claim 1 further comprising a dielectric layer formed between said gate dielectric layer and conductive electrode layer.

4. The FET of claim 1 further comprising a dielectric layer formed between said channel and said gate dielectric layer.

5. The FET of claim 1 further comprising a dielectric layer formed between the channel and the ferroelectric regions of said gate dielectric layer.

6. The FET of claim 1 further comprising a dielectric layer formed between said conductive layer and the ferroelectric regions of said gate dielectric layer.

7. The FET of claim 3 wherein the dielectric layer comprises silicon nitride.

8. The FET of claim 4 wherein the dielectric layer comprises silicon nitride.

9. The FET of claim 5 wherein the dielectric layer comprises silicon nitride.

10. The FET of claim 6 wherein the dielectric layer comprises silicon nitride.

11. The FET of claim 3 wherein the dielectric layer comprises silicon dioxide.

12. The FET of claim 4 wherein the dielectric layer comprises silicon dioxide.

13. The FET of claim 5 wherein the dielectric layer comprises silicon dioxide.

14. The FET of claim 6 wherein the dielectric layer comprises silicon dioxide.

15. The FET of claim 3 wherein the dielectric layer comprises thermally grown silicon dioxide.

16. The FET of claim 4 wherein the dielectric layer comprises thermally grown silicon dioxide.

17. The FET of claim 5 wherein the dielectric layer comprises thermally grown silicon dioxide.

18. The FET of claim 6 wherein the dielectric layer comprises thermally grown silicon dioxide.

19. The FET of claim 3 wherein the dielectric layer comprises two or more dielectric sub-layers.

20. The FET of claim 4 wherein the dielectric layer comprises two or more dielectric sub-layers.

21. The FET of claim 5 wherein the dielectric layer comprises two or more dielectric sub-layers.

22. The FET of claim 6 wherein the dielectric layer comprises two or more dielectric sub-layers.

23. The FET of claim 3 wherein the dielectric layer comprises a silicon nitride layer overlying a silicon dioxide layer.

24. The FET of claim 4 wherein the dielectric layer comprises a silicon nitride layer overlying a silicon dioxide layer.

25. The FET of claim 5 wherein the dielectric layer comprises a silicon nitride layer overlying a silicon dioxide layer.

26. The FET of claim 6 wherein the dielectric layer comprises a silicon nitride layer overlying a silicon dioxide layer.

27. The FET of claim 1 wherein the conductive electrode layer comprises a polysilicon-containing material

28. The FET of claim 1 wherein the ferroelectric layer comprises a material having the general formula A_xMn_yO_z where x, y, z vary from 0.1 to 10 and A is a rare earth selected from a group consisting of Ce, Pr, Nd, Pm, Sm, Eu, GD, Tb, Dy, Ho, Er, Tm, Yb, Lu, Y or Sc.

29. The FET of claim 1 wherein the ferroelectric layer comprises a low-dielectric ferroelectric material.

30. The FET of claim 1 wherein the ferroelectric layer is formed utilizing MOCVD.

31. The FET of claim 3 wherein the dielectric layer is formed utilizing MOCVD.

32. The FET of claim 3 wherein the dielectric layer is formed utilizing ALD.

33. The FET of claim 4 wherein the dielectric layer is formed utilizing MOCVD.

34. The FET of claim 4 wherein the dielectric layer is formed utilizing ALD.

35. The FET of claim 5 wherein the dielectric layer is formed utilizing MOCVD.

36. The FET of claim 5 wherein the dielectric layer is formed utilizing ALD.

37. The FET of claim 6 wherein the dielectric layer is formed utilizing MOCVD.

38. The FET of claim 6 wherein the dielectric layer is formed utilizing ALD.

39. The FET of claim 3 wherein the dielectric layer comprises a material with a dielectric constant of 10 and greater.

40. The FET of claim 4 wherein the dielectric layer comprises a material with a dielectric constant of 10 and greater.

41. The FET of claim 5 wherein the dielectric layer comprises a material with a dielectric constant of 10 and greater.

42. The FET of claim 6 wherein the dielectric layer comprises a material with a dielectric constant of 10 and greater.

43. The FET of claim 1 wherein the silicon substrate comprises a CMOS compatible substrate.

44. The FET of claim 1 wherein the silicon substrate comprises a silicon-on-insulator substrate.

45. A method for the non-volatile storage of two data bits in a single FET transistor comprising:

providing a field effect transistor (FET) having gate, drain, source, and substrate terminals, and having a first ferroelectric region between the gate and substrate in the source region and second ferroelectric region between the gate and the substrate in the drain region;

applying a positive voltage greater than the coercive voltage between the gate and the source to polarize said first ferroelectric region to a first state;

applying a negative voltage greater than the coercive voltage between the gate and source to polarize said first ferroelectric region to a second state;

applying a positive voltage greater than the coercive voltage between the gate and the drain to polarize said second ferroelectric region to the first state;

applying a negative voltage greater than the coercive voltage between the gate and the drain to polarize said second ferroelectric region to the second state;

applying a positive voltage less than the coercive voltage on the gate, ground potential on the source, and a positive voltage no greater than the gate voltage on the drain to detect the polarization state of said first ferroelectric region, a high current between source and drain indicating the first state and a low current between source and drain indicating the second state; and

applying a positive voltage less than the coercive voltage on the gate, ground potential on the drain, and a positive voltage no greater than the gate voltage on the source to detect the polarization state of said second ferroelectric region, a high current between source and drain indicating the first state and a low current between source and drain indicating the second state.

46. A non-volatile memory storage method comprising:

providing an array of field effect transistors (FETs), wherein each FET in the array has a gate, drain, source, and substrate terminals, a first ferroelectric region between the gate and substrate in the source region, and a second ferroelectric region between the gate and the substrate in the drain region, wherein the array is arranged in rows and columns, the gates of the FETs in a same row being coupled to a word line, the sources of FETs in a same column being coupled to a source bit line, and the drains of FETs in a same column being coupled to a drain bit line;

applying a positive voltage to a selected word line, a negative voltage on a selected source bit line, ground potential on unselected word lines, unselected source lines and all drain bit lines such that a voltage greater that the coercive voltage is applied between the selected word line and selected source line, but a voltage less than the coercive voltage is applied between unselected word lines and selected source bit lines, between unselected word lines and unselected source bit lines, between unselected word lines and drain bit lines, selected word lines and drain bit lines, and selected word lines and unselected source bit lines to polarize said first ferroelectric region of a selected FET to a first state while leaving the polarization of all other ferroelectric materials in the array unchanged;

applying a negative voltage to the selected word line, a positive voltage on the selected source bit line, ground potential on unselected word lines, unselected source lines and all drain bit lines such that a voltage greater that the coercive voltage is applied between the selected word line and selected source line, but a voltage less than the coercive voltage is applied between unselected word lines and selected source bit lines, between unselected word lines and unselected source bit lines, between unselected word lines and drain bit lines, selected word lines and drain bit lines, and selected word lines and unselected source bit lines to polarize said first ferroelectric region of the selected FET to a second state while leaving the polarization of all other ferroelectric materials in the array unchanged;

applying a positive voltage to the selected word line, a negative voltage on the selected drain bit line, ground potential on unselected word lines, unselected drain lines and all source bit lines such that a voltage greater that the coercive voltage is applied between the selected word line and selected drain line, but a voltage less than the coercive voltage is applied between unselected word lines and selected drain bit lines, between unselected word lines and unselected drain bit lines, between unselected word lines and source bit lines, selected word lines and source bit lines, and selected word lines and unselected drain bit lines to polarize said second ferroelectric material of the selected FET to the first state while leaving the polarization of all other ferroelectric materials in the array unchanged;

applying a negative voltage to the selected word line, a positive voltage on the selected drain bit line, ground potential on unselected word lines, unselected drain lines and all source bit lines such that a voltage greater that the coercive voltage is applied between the selected word line and selected drain line, but a voltage less than the coercive voltage is applied between unselected word lines and selected drain bit lines, between unselected word lines and unselected drain bit lines, between unselected word lines and source bit lines, selected word lines and source bit lines, and selected word lines and unselected drain bit lines to polarize said second ferroelectric material of the selected FET to second state while leaving the polarization of all other ferroelectric materials in the array unchanged;

applying a positive voltage less the coercive voltage on the selected word line, ground potential on the selected source bit line, a positive voltage no greater than the word line voltage on the selected drain bit line, and ground potential on unselected word lines, unselected source bit lines, and unselected drain bit lines to detect the polarization state of said first ferroelectric region, a high current between the selected source bit line and the selected drain bit line indicating first state and a low current between selected source bit line and selected drain bit line indicating the second state; and

applying a positive voltage less the coercive voltage on the selected word line, ground potential on the selected drain bit line, a positive voltage no greater than the word line voltage on the selected source bit line, and ground potential on unselected word lines, unselected source bit lines, and unselected drain bit lines to detect the polarization state of said second ferroelectric region, a high current between selected drain bit line and selected source bit line indicating first state and a low current between selected drain bit line and selected source bit line indicating second state.

47. A ferroelectric field effect transistor comprising:

a source, a gate, a drain, and a channel;

a gate dielectric layer including a first ferroelectric region overlaying the channel in the vicinity of the source, a second ferroelectric region overlaying the channel in the vicinity of the drain, and a non-ferroelectric dielectric overlaying the channel between the first and second ferroelectric region; and

a conductive electrode layer overlaying said gate layer.

48. A ferroelectric field effect transistor comprising a source, a gate, a drain, and a gate dielectric layer including distinct first and second ferroelectric regions that are separately polarized representing two data bits.

49. A method for the non-volatile storage of two data bits in a single FET transistor comprising:

providing a field effect transistor (FET) having a gate, drain, source, and substrate, and having a first ferroelectric region between the gate and the substrate in the source region and a second ferroelectric region between the gate and the substrate in the drain region;

selectively applying a voltage greater than a coercive voltage across the gate and the source to polarize said first ferroelectric region;

selectively applying a voltage greater than the coercive voltage across the gate and the drain to polarize said second ferroelectric region;

applying a positive voltage less than the coercive voltage on the gate, ground potential on the source, and a positive voltage no greater than the gate voltage on the drain to detect the polarization state of said first ferroelectric region; and

applying a positive voltage less than the coercive voltage on the gate, ground potential on the drain, and a positive voltage no greater than the gate voltage on the source to detect the polarization state of said second ferroelectric region.

50. A non-volatile memory storage method comprising:

providing an array of field effect transistors (FETs), wherein each FET in the array has a gate, drain, source, and substrate terminals, a first ferroelectric region between the gate and substrate in the source region, and a second ferroelectric region between the gate and the substrate in the drain region, wherein the array is arranged in rows and columns, the gates of the FETs in a same row being coupled to a word line, the sources of FETs in a same column being coupled to a source bit line, and the drains of FETs in a same column being coupled to a drain bit line;

applying a voltage greater that the coercive voltage across a selected word line and a selected source line to polarize said first ferroelectric region of a selected FET while leaving the polarization of all other ferroelectric materials in the array unchanged;

applying a voltage greater that the coercive voltage across the selected word line and a selected drain line to polarize said second ferroelectric region of the selected FET while leaving the polarization of all other ferroelectric materials in the array unchanged;

applying a positive voltage less the coercive voltage on the selected word line, ground potential on the selected source bit line, a positive voltage no greater than the word line voltage on the selected drain bit line to detect the polarization state of said first ferroelectric region; and

applying a positive voltage less the coercive voltage on the selected word line, ground potential on the selected drain bit line, a positive voltage no greater than the word line voltage on the selected source bit line to detect the polarization state of said second ferroelectric region.