Magnetic random access memory

• US 20040057277A1
• Filed: 02/20/2003
• Published: 03/25/2004
• Est. Priority Date: 09/25/2002
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Fujita, Katsuyuki, Iwata, Yoshihisa
• Granted Patent: US 6,819,585 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

One end of a write word line is connected to a decoder/driver unit. The decoder/driver unit is constituted by a P channel MOS transistor, an N channel MOS transistor, and an NAND circuit. When WRITE, CHRDY and RA1 all become “H”, an output signal from the NAND circuit becomes “H”, and a write current flows through the write word line. CHRDY is a signal which becomes “H” upon completion of an initialization operation of all internal circuits after turning on a power supply. A limiting circuit is constituted by a clamp circuit which limits a potential of a write word line to a fixed value or a lower value.

Claims

1. A magnetic random access memory comprising:

a memory cell array determining an element having a magnetic layer as a memory cell;

a first write line used to write data in said memory cell;

a first decoder which selects said first write line based on a first address signal; and

a first driver which is connected to one end of said first write line, and supplies a write current to said first write line when said first write line is selected by said first decoder,

wherein said first decoder is maintained in a non-active state until an initialization operation of an internal circuit is completed after turning on a power supply.

2. The magnetic random access memory according to claim 1, further comprising:

a power-on detection circuit which outputs a signal indicative of completion of said initialization operation of said internal circuit,

wherein said first decoder enters an active state upon receiving said signal.

3. The magnetic random access memory according to claim 1, further comprising:

a limiting circuit which is connected to said first write line and limits a potential generated in said first write line to a fixed value or a lower value.

4. The magnetic random access memory according to claim 3, wherein said limiting circuit is constituted by at least one of a MOS transistor or a diode.

5. The magnetic random access memory according to claim 1, further comprising:

a second write line which is used to write data in said memory cell and crosses said first line;

a second decoder which selects said second write line based on a second address signal; and

a second driver which is connected to one end of said second write line, and supplies a write current to said second write line when said second write line is selected by said second decoder,

wherein said second decoder is maintained in said non-active state until said initialization operation of said internal circuit is completed after turning on said power supply.

6. The magnetic random access memory according to claim 5, further comprising:

a third decoder which selects said second write line based on said second address signal; and

a third driver which is connected to the other end of said second write line, and supplies a write current to said second write line when said second write line is selected by said third decoder,

wherein said third decoder is maintained in said non-active state until said initialization operation of said internal circuit is completed after tuning on said power supply.

7. The magnetic random access memory according to claim 6, wherein said first write line is a write word line, said first driver is a write word line driver, said second write line is a write bit line, and said second and third drivers are write bit line drivers.

8. The magnetic random access memory according to claim 6, further comprising:

a power-on detection circuit which outputs a signal indicative of completion of said initialization operation of said internal circuit,

wherein said first, second and third decoders enter said active state upon receiving said signal.

9. The magnetic random access memory according to claim 6, further comprising:

a first limiting circuit which is connected to said first write line, and limits a potential generated in said first write line to a fixed value or a lower value; and

a second limiting circuit which is connected to said second write line, and limits a potential generated in said second write line to a fixed value or a lower value.

10. The magnetic random access memory according to claim 9, wherein each of said first and second limiting circuits is constituted by at least one of an MOS transistor and a diode.

11. The magnetic random access memory according to claim 9, wherein said memory cell array has a cross point type cell array structure.