Non-volatile memory and method with reduced neighboring field errors

• US 20040057285A1
• Filed: 09/24/2002
• Published: 03/25/2004
• Est. Priority Date: 09/24/2002
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Cernea, Raul-Adrian, Li, Yan
• Granted Patent: US 6,987,693 B2
• Time in Patent Office: Days
• US Class Current: 365/185.12
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A memory device and a method thereof allow programming and sensing a plurality of memory cells in parallel in order to minimize errors caused by coupling from fields of neighboring cells and to improve performance. The memory device and method have the plurality of memory cells linked by the same word line and a read/write circuit is coupled to each memory cells in a contiguous manner. Thus, a memory cell and its neighbors are programmed together and the field environment for each memory cell relative to its neighbors during programming and subsequent reading is less varying. This improves performance and reduces errors caused by coupling from fields of neighboring cells, as compared to conventional architectures and methods in which cells on even columns are programmed independently of cells in odd columns.

Claims

1. A method of programming a plurality of non-volatile memory cells in parallel with reduced error due to perturbing electric fields from neighboring memory cells, comprising:

(a) organizing said plurality of memory cells into a page of contiguous memory cells linked by a word line;

(b) coupling a read/write circuit to each memory cell of said page of contiguous memory cells;

(c) sensing said each memory cell in parallel to verify its memory state relative to one to be programmed;

(d) inhibiting said each memory cell among said page that has been verified;

(e) applying a programming pulse to said page of contiguous memory cells; and

(f) repeating steps (c)-(e) until all memory cells of said page have been verified.

2. The programming method as in claim 1, wherein:

said page of contiguous memory cells forms a row of a memory array; and

said row is linked by a word line.

3. The programming method as in claim 1, wherein:

said page of contiguous memory cells forms a portion of a row of a memory array; and

said row is linked by a word line.

4. The programming method as in claim 3, wherein said page of contiguous memory cells forms one half of a row of a memory array.

5. The programming method as in claim 4, wherein two of said pages of contiguous memory cells form a row of a memory array.

6. The programming method as in claim 5, wherein:

the memory array is accessible by a set of bit lines; and

said programming method further comprises;

programming one of said two pages; and

grounding the bit lines of memory cells not being programmed.

7. The programming method as in claim 3, wherein:

the memory array is accessible by a set of bit lines; and

said programming method further comprises;

programming said portion of a row of contiguous memory cells; and

grounding the bit lines of memory cells not being programmed.

8. The programming method as in any one of claims 1-7, wherein said plurality of memory cells is constituted from flash EEPROM cells.

9. The programming method as in any one of claims 1-7, wherein said plurality of memory cells is constituted from NROM cells.

10. The programming method as in any one of claims 1-7, wherein each memory cell stores one bit of data.

11. The programming method as in any one of claims 1-7, wherein each memory cell stores more than one bit of data.

12. A non-volatile memory device, comprising:

an array of memory cells, addressable row by row by a set of word lines and column by column by a set of bit lines; and

a read/write circuit, addressable to coupled to each of a contiguous segment of memory cells linked by a word line in a row, such that said memory cells in said contiguous segment are read or programmed together.

13. The non-volatile memory device as in claim 12, wherein:

said contiguous segment of memory cells forms a row of said memory array; and

said row is linked by a word line.

14. The non-volatile memory device as in any one of claims 12-13, wherein said plurality of memory cells is constituted from flash EEPROM cells.

15. The non-volatile memory device as in any one of claims 12-13, wherein said plurality of memory cells is constituted from NROM cells.

16. The non-volatile memory device as in any one of claims 12-13, wherein each memory cell stores one bit of data.

17. The non-volatile memory device as in any one of claims 12-13, wherein each memory cell stores more than one bit of data.

18. The non-volatile memory device as in claim 12, further comprising:

means for grounding the bit lines of memory cells not addressed for reading or programming.

19. The non-volatile memory device as in claim 18, wherein said contiguous segment of memory cells forms a portion of a row of a memory array.

20. The non-volatile memory device as in claim 19, wherein said contiguous segment of memory cells forms one half of a row of a memory array.

21. The non-volatile memory device as in claim 20, wherein two of said contiguous segment of memory cells forms a row of a memory array.

22. The non-volatile memory device as in any one of claims 18-21, wherein

said plurality of memory cells is constituted from flash EEPROM cells.

23. The non-volatile memory device as in any one of claims 18-21, wherein said plurality of memory cells is constituted from NROM cells.

24. The non-volatile memory device as in any one of claims 18-21, wherein each memory cell stores one bit of data.

25. The non-volatile memory device as in any one of claims 18-21, wherein each memory cell stores more than one bit of data.