System and method for transferring data among transceivers substantially void of data dependent jitter

• US 20040057542A1
• Filed: 09/24/2002
• Published: 03/25/2004
• Est. Priority Date: 09/24/2002
• Status: Active Grant

• Current Assignee: Standard Microsystems Corporation (Microchip Technology Incorporated)
• Original Assignee: Standard Microsystems Corporation (Microchip Technology Incorporated)
• Inventors: Knapp, David J., Lewis, Jason E.
• Granted Patent: US 7,664,214 B2
• Time in Patent Office: Days
• US Class Current: 375/355
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H04L 7/0079 Receiver details
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/04 Speed or phase control by synchronisation signals H04L7/0075 takes precedence
• CPC Class Codes: H04L 7/08 the synchronisation signals recurring cyclically

Abstract

A communication system, clock generation circuit, and method are provided for receiving jitter upon data and to generate a clock reference that does not contain the received jitter. The clock reference can be used either by a digital subsystem of a communication system node, or can be transmitted as substantially jitter-free data from that node to a downstream node of the communication system. Instead of recovering the clock reference from the data having jitter, a pattern is regularly defined within the data stream preferably at periodic, timed intervals. The data pattern may be made up of a series of non-transitions which, regardless of any jitter in the data itself, does not impute any jitter onto a phase-locked loop triggered from an edge of the non-transitioning data pattern. Using the edge as a reference point, a jitter-free clocking signal can be derived at the same frequency as a clocking signal which would normally be produced from the jitter-induced data.

Claims

1. A clock generation circuit, comprising:

a detection circuit coupled to receive a stream of data having a pattern of data interspersed within the stream of data, and to generate an edge during a time in which the pattern of data ends; and

an oscillator coupled to generate a plurality of regularly spaced clock pulses phase synchronized to the edge.

2. The clock generation circuit as recited in claim 1, wherein the detection circuit comprises a comparator coupled to produce the edge at the same time regardless of a rate at which the data preceding the pattern of data transitions.

3. The clock generation circuit as recited in claim 1, wherein the detection circuit comprises a comparator coupled to produce the edge at the same time regardless of whether the stream of data preceding the pattern of data is encoded as a logic one, logic zero, or random logic value.

4. The clock generation circuit as recited in claim 1, wherein the detection circuit comprises:

a first logic gate coupled to output the edge independent of a polarity of the pattern of data; and

a second logic gate coupled to receive the output from the first logic gate during a window pulse that repeats at least one time during which the pattern of data repeats.

5. The clock generation circuit as recited in claim 1, wherein the pattern of data extends for a duration exceeding the reciprocal of the cutoff frequency of a low-pass filter associated with the detection circuit.

6. The clock generation circuit as recited in claim 1, wherein the pattern of data extends for a duration that ensures voltage output from the detection circuit achieves the same value at the end of the pattern independent of any preceding data.

7. The clock generation circuit as recited in claim 1, wherein the pattern of data extends during a preamble between frames of the stream of data.

8. The clock generation circuit as recited in claim 1, wherein the pattern of data extends for a time period indicative of a coding violation, and wherein the detection circuit is adapted to detect the coding violation.

9. The clock generation circuit as recited in claim 1, wherein the regularly spaced clock pulses are forwarded to a digital circuit for synchronizing operation thereof.

10. The clock generation circuit as recited in claim 1, further comprising:

a first phase-locked loop coupled to receive the stream of data and generate a first clock therefrom;

a second phase-locked loop having a phase detector that aligns at least one phase of the regularly spaced clock pulses with the edge to form a second clock therefrom; and

a buffer coupled to receive the stream of data synchronized to the first clock and to output the stream of data to a digital circuit synchronized to the second clock.

11. The clock generation circuit as recited in claim 1, wherein the detection circuit comprises:

a window state machine coupled to receive a first clock generated from the stream of data and to produce a window pulse synchronized to the first clock and having a duration that begins prior to the edge and ends after the edge; and

logic coupled to produce the edge only during times when the window pulse exist.

12. A communication system, comprising:

a receiver coupled to receive a pattern of bit values within a data stream and to generate an edge from each said pattern to which one of a plurality of regular clock pulses are generated in phase with the edge; and

a synchronous circuit coupled to process data synchronized to the plurality of regular clock pulses.

13. The communication system as recited in claim 12, wherein the synchronous circuit comprises a transmitter coupled to transmit the data synchronized to the plurality of regular clock pulses.

14. The communication system as recited in claim 12, wherein the synchronous circuit comprises a multimedia device.

15. The communication system as recited in claim 12, wherein the receiver comprises:

a window state machine coupled to produce a window pulse synchronized to a first clock generated from the data stream, beginning before the edge and ending after the edge; and

logic coupled to produce the edge only during times when the window pulse exists.

16. The communication system as recited in claim 12, wherein the receiver comprises a detection circuit coupled to detect logic value transitions of the data stream and to

produce a relatively variable output depending on a logic value of the data stream, and

produce a relatively fixed output at the culmination of the pattern of bit values.

17. The communication system as recited in claim 12, wherein the pattern of bit values correspond to a coding violation.

18. The communication system as recited in claim 12, wherein a reciprocal of the time duration of pattern of bit values is less than the cutoff frequency of the receiver.

19. A method for transferring data substantially free of jitter, comprising generating an edge at the same time relative to an end of a pattern of bit values placed periodically within a stream of data.

20. The method as recited in claim 19, further comprising:

receiving the stream of data transitioning at a rate dependent on a logic value of the data;

compiling a first clocking signal having jitter dependent on a frequency at which the rate changes;

compiling a second clocking signal synchronized to the edge and having regularly occurring pulses transitioning at substantially the same rate as the first clocking signal; and

transferring the data synchronized to the second clocking signal.

21. The method as recited in claim. 20, wherein said receiving and compiling steps occur within a first transceiver and said transferring step occurs within a communication link coupled between the first transceiver and a second transceiver of a communication system.

22. The method as recited in claim 20, wherein said transferring comprises operating a digital system synchronized to the second clocking signal.