Wafer bonding hermetic encapsulation

• US 20040058476A1
• Filed: 09/25/2002
• Published: 03/25/2004
• Est. Priority Date: 09/25/2002
• Status: Active Grant

• Current Assignee: Invensas Bonding Technologies, Inc. (Adeia Inc.)
• Original Assignee: Ziptronix Incorporated (Adeia Inc.)
• Inventors: Enquist, Paul M., Tong, Qin-Yi, Fountain, Gaius Gillman Jr., Markunas, Robert
• Granted Patent: US 6,822,326 B2
• Time in Patent Office: Days
• US Class Current: 438/114
• CPC Class Codes: B81C 1/00269 Bonding of solid lids or wafers to the substrate
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01079 Gold [Au]

Abstract

A method for providing encapsulation of an electronic device which obtains an encapsulating member configured to enclose the electronic device, prepares a surface of the encapsulating member for non-adhesive direct bonding, prepares a surface of a device carrier including the electronic device for non-adhesive direct bonding, and bonds the prepared surface of the encapsulating member to the prepared surface of the device carrier to form an encapsulation of the electronic device. As such, an encapsulated electronic device results which includes the device carrier having a first bonding region encompassing the electronic device, includes the encapsulating member having at least one relief preventing contact between the electronic device and the encapsulating member and having a second bonding region bonded to the first bonding region of the device carrier, and includes a non-adhesive direct bond formed between the first and second bonding regions thereby to form an encapsulation of the electronic device. The encapsulated electronic device can be an electronic or optoelectronic device.

Claims

1. A method for packaging a device, comprising:

obtaining an encapsulating member configured to enclose said device;

preparing a surface of said encapsulating member for non-adhesive direct bonding;

preparing a surface area of a device carrier including the device for non-adhesive direct bonding; and

bonding at near room temperature said prepared surface of the encapsulating member to said prepared surface of the device carrier to form an encapsulation of said device.

2. A method as recited in claim 1, wherein said bonding comprises hermetically encapsulating said device.

3. A method as recited in claim 1, wherein said device carrier comprises a substrate, said device formed on said substrate, said method comprising:

preparing a surface area of said substrate for non-adhesive direct bonding before fabricating said device;

protecting said surface of said substrate during fabrication of said device such that surface roughness characteristics of said surface of said substrate are not significantly degraded during said fabrication.

4. A method as recited in claim 3, wherein:

said protecting comprises fabricating said device in a manner where surface roughness characteristics of said surface area are not significantly degraded.

5. A method as recited in claim 3, wherein:

preparing said surface area comprises obtaining a surface roughness of said surface area in a range of about 0.5-1 nm; and

said protecting step comprises maintaining said surface roughness in said range.

6. A method as recited in claim 3, wherein:

said protecting comprises forming a protective layer on said surface area of said substrate.

7. A method as recited in claim 6, comprising:

removing said protective layer after substantially completing fabricating said device.

8. A method as recited in claim 1, wherein:

preparing said surface area comprises forming a first bonding layer on said surface area; and

bonding comprises bonding said prepared surface of said encapsulating member to a surface of said first bonding layer.

9. A method as recited in claim 8, wherein:

said protecting comprises forming a protective layer on said first bonding layer.

10. A method as recited in claim 9, comprising:

removing said protective layer after substantially completing fabricating said device.

11. A method as recited in claim 8, comprising:

preparing said surface of said first bonding layer for non-adhesive direct bonding.

12. A method as recited in claim 11, comprising:

preparing said surface of said first bonding layer and said surface area of said device carrier each to have a surface roughness in a range of no more than about 0.5-1.0 nm.

13. A method as recited in claim 12, comprising:

activating said surface of said first bonding layer; and

activating said surface area of said device carrier.

14. A method as recited in claim 13, wherein each of said activating steps comprises an etching process where a surface roughness of said surface of said bonding layer and a surface roughness of said surface area of said device carrier before and after said etching are each substantially the same.

15. A method as recited in claim 8, wherein:

preparing said surface area comprises forming a second bonding layer on said surface area; and

bonding comprises bonding said first bonding layer to said second bonding layer.

16. A method as recited in claim 15, wherein forming said first and second bonding layers comprises forming a silicon oxide film.

17. A method as recited in claim 15, wherein forming at least one of said first and second bonding layers comprises ion implanting at least one of oxygen and nitrogen into said surface of said encapsulating member and said surface area of said device carrier, respectively.

18. A method as recited in claim 1, comprising:

preparing said surface of said first bonding layer and said surface area of said device carrier each to have a surface roughness in a range of no more than about 0.5-1.0 nm;

activating said surface of said first bonding layer; and

activating said surface area of said device carrier.

19. A method as recited in claim 1, wherein:

preparing said surface area comprises forming a bonding layer on said encapsulating member; and

bonding comprises bonding said bonding layer to said surface area.

20. A method as recited in claim 1, wherein said encapsulating member is a substrate having one of an active device, circuit, circuit element and integrated circuit formed therein.

21. A method as recited in claim 20, comprising:

connecting said one of an active device, circuit, circuit element and integrated circuit to said device.

22. A method as recited in claim 21, comprising:

forming an aperture through said encapsulating member to over said surface area; and

connecting said one of an active device, circuit, circuit element and integrated circuit to said device through said aperture.

23. A method as recited in claim 21, comprising:

forming an aperture through said encapsulating member over said device; and

connecting said one of an active device, circuit, circuit element and integrated circuit to said device through said aperture.

24. A method as recited in claim 21, comprising:

forming said encapsulating member to have a region over said surface area and separated from said surface area by a gap;

forming an aperture in said encapsulating member in said region over said surface area; and

connecting said one of an active device, circuit, circuit element and integrated circuit to said device through said aperture.

25. A method as recited in claim 24, comprising:

hermetically sealing said device.

26. A method as recited in claim 24, comprising:

placing said bonded encapsulating member and device carrier in a vacuum after forming said aperture; and

performing said connecting in said vacuum.

27. A method as recited in claim 24, comprising:

forming said encapsulating member to have a gap of approximately between 0.1 and 1.0 microns.

28. A method as recited in claim 21, comprising:

forming said encapsulating member to have an extended portion located over said device and separated from said device by a gap; and

forming an aperture through said extended portion; and

connecting said one of an active device, circuit, circuit element and integrated circuit to said device through said aperture.

29. A method as recited in claim 28, comprising:

forming said encapsulating member to have said extended portion located over a conducting portion of said device.

30. A method as recited in claim 21, comprising:

forming said encapsulating member to have an extended portion located over said device and contacting said device, said extended portion not being bonded to said device; and

forming an aperture through said extended portion; and

connecting said one of an active device, circuit, circuit element and integrated circuit to said device through said aperture.

31. A method as recited in claim 30, comprising:

forming said encapsulating member to have said extended portion located over a conducting portion of said device.

32. A method as recited in claim 1, comprising:

forming a plurality of contacts to said device through said encapsulating member.

33. A method as recited in claim 1, comprising:

preparing said surface area to a surface roughness no more than about 0.5-1 nm; and

preparing said surface of said device carrier to a surface roughness no more than about 0.5-1 nm.

34. A method as recited in claim 1, wherein said obtaining an encapsulating member comprises:

providing in said encapsulating member a relief configured upon said bonding to provide clearance from said device.

35. A method as recited in claim 1, comprising:

forming a cavity in said encapsulating member with a pattern contoured in relation to the device; and

bonding said encapsulating member to said device carrier with said cavity positioned to oppose said device.

36. A method as recited in claim 1, wherein obtaining said encapsulating member comprises:

forming material on a plate to produce a cavity; and

bonding said material to said device carrier with said cavity positioned to oppose said device.

37. A method as recited in claim 1, wherein obtaining said encapsulating member comprises:

obtaining an interposer having at least one through hole; and

bonding a cover to said interposer.

38. The method as recited in claim 1, wherein obtaining said encapsulating member comprises:

preparing a surface of a plate for non-adhesive direct bonding;

preparing a surface of an interposer for non-adhesive direct bonding; and

bonding said interposer to said plate.

39. A method as recited in claim 38, wherein obtaining said encapsulating member comprises:

placing said interposer on said device carrier;

placing said plate on said interposer; and

bonding at the same time said interposer to said device carrier and said interposer to said plate.

40. A method as recited in claim 1, wherein preparing said surface of said encapsulating member and preparing said surface area each comprises at least one of grinding, chemical mechanical polishing, and etching.

41. A method as recited in claim 1, comprising:

providing as said encapsulating member a cover configured to encapsulate a recessed device located in a recess of said device carrier; and

bonding a surface of said cover to said surface of said device carrier.

42. A method as recited in claim 41, wherein said cover comprises a semiconductor wafer having a semiconductor device formed therein.

43. A method as recited in claim 1, comprising:

preparing said surface of said encapsulating member and said surface area of said device carrier each to have a surface roughness in a range of no more than about 0.5-1.0 nm; and

activating said surface of said encapsulating layer; and

activating said surface area of said device carrier.

44. A method as recited in claim 43, wherein said activating comprises:

immersing at least one of said surface of said encapsulating layer and said surface area in a solution.

45. A method as recited in claim 44, wherein said immersing forms on said at least one of said surface of said encapsulating layer and said surface area a species including at least one of a silanol group, an NH₂ group, a fluorine group, and an HF group.

46. A method as recited in claim 43, wherein said activating comprises:

exposing said at least one of said surface of said encapsulating layer and said surface area to a plasma.

47. A method as recited in claim 46, wherein said exposing to a plasma comprises:

exposing said at least one of said surface of said encapsulating layer and said surface area to one of an oxygen, argon, NH₃ and CF₄ plasma process.

48. A method as recited in claim 47, wherein said exposing to a plasma comprises:

conducting said plasma process in one of a reactive ion etch mode, inductively coupled plasma mode, and a sputtering mode.

49. A method as recited in claim 43, wherein said activating produces a surface having bonding groups capable of forming chemical bonds between the encapsulating member and the device carrier at approximately room temperature.

50. A method as recited in claim 49, comprising forming a chemical bond of at least 500 mJ/m².

51. A method as recited in claim 49, comprising forming a chemical bond of a range of 500-2000 mJ/m².

52. A method as recited in claim 1, wherein at least one of preparing said surface of said encapsulating member and preparing said surface area of said device carrier comprises:

depositing a polishable material.

53. A method as recited in claim 52, wherein depositing said polishable material comprises depositing at least one of silicon oxide, aluminum oxide, silicon nitride, a spin-on glass, and a dielectric polymer.

54. A method as recited in claim 1, comprising:

annealing the non-adhesive direct bond to increase a bond strength between said encapsulating member and said device carrier.

55. A method as recited in claim 1, comprising:

encapsulating at least one of an optoelectronic device, a micro-electrical mechanical systems MEMS device, and a radio frequency device.

56. A method as recited in claim 55, comprising:

encapsulating a concave device.

57. A method as recited in claim 55, comprising:

encapsulating a MEMS concave device.

58. A method as recited in claim 55, comprising:

encapsulating a plurality of concave devices.

59. A method as recited in claim 58, wherein encapsulating a plurality of concave devices compartmentalizes each of said plurality of concave devices.

60. A method as recited in claim 55, comprising:

encapsulating a convex device.

61. A method as recited in claim 55, comprising:

encapsulating a convex MEMS device.

62. A method as recited in claim 61, comprising:

encapsulating a plurality of convex devices.

63. A method as recited in claim 62, wherein encapsulating a plurality of convex devices compartmentalizes each of said plurality of convex devices.

64. A method as recited in claim 1, comprising:

forming an interconnection to said device through said device carrier.

65. A method as recited in claim 1, comprising:

forming an interconnection through a side of said encapsulating member.

66. A method as recited in claim 65, further comprising:

providing an opening in a wall of said encapsulating member prior to said bonding such that an interconnect connected to said device is not contacted by and encapsulating member upon said bonding; and

metallizing said opening to complete said encapsulation of said device.

67. A method as recited in claim 66, wherein the metallizing comprises:

electroplating the interconnect to fill said opening.

68. A method as recited in claim 66, wherein the metallizing comprises:

depositing metal selectively on the interconnect to fill said opening.

69. A method as recited in claim 65, wherein forming an interconnection comprises:

forming at least one of an electrical interconnection and an optical interconnection underneath said surface area of said device carrier.

70. A method as recited in claim 1, further comprising:

etching a trench on said surface area of said device carrier prior to said bonding;

depositing a metal/dielectric/metal structure in said trench such that an interleaving dielectric layer of the metal/dielectric/metal structure is substantially planar with said surface area of said device carrier and a metal layer of the metal/dielectric/metal structure connects to a lead of said device; and

bonding said prepared surface of said encapsulating member to a portion of said interleaving dielectric layer.

71. A method as recited in claim 1, further comprising:

depositing a metal/dielectric/metal structure on said surface area of said device carrier such that metal of the metal/dielectric/metal structure connects to a metal lead of said device and said dielectric has a surface roughness of less than 0.5-1 nm and a surface planarity of less than 0.1 μ

m over a 100 μ

m range, and

bonding said surface of the encapsulation member to said dielectric to form said encapsulation.

72. A method as recited in claim 1, further comprising:

depositing a metal/dielectric/metal structure on said surface area of said device carrier such that metal of the metal/dielectric/metal structure connects to a lead of said device;

depositing a planarization dielectric on said surface of the device carrier and on said interlevel metal/dielectric/metal structure to planarize a portion of said surface area of said device carrier for said non-adhesive direct bonding; and

bonding said surface of the encapsulating member to the planarization dielectric during to form said encapsulation.

73. A method as recited in claim 1, further comprising:

etching a trench on said surface area of the device carrier prior to said bonding;

depositing an optical fiber in said trench;

filling said trench with a planarizing dielectric; and

bonding said prepared surface of said encapsulating member to a planarized portion of said dielectric.

74. A method as recited in claim 1, further comprising:

etching a trench on said surface area of said device carrier prior to said bonding;

depositing an optical fiber in said trench;

filling said trench with a metal;

planarizing the metal; and

bonding said prepared surface of said encapsulating member to a planarized portion of said metal.

75. A method as recited in claim 1, comprising:

bonding said encapsulation member to said surface area of said device carrier over a region on said device carrier where an interconnection to said device is desired.

76. A method as recited in claim 75, comprising:

forming a via through said encapsulation member to said surface area of said device carrier over said region on the device carrier where an interconnection is desired without adversely compromising the encapsulating integrity of the encapsulating member.

77. A method as recited in claim 75, wherein bonding said encapsulating member to said surface area of said device carrier comprises bonding said encapsulating member to a conductive surface region in said surface area forming an interconnection to said device.

78. A method as recited in claim 75, comprising:

bonding said encapsulation member to a non-conductive region in said surface area;

forming an opening in said non-conductive region to expose a conductive element; and

forming said interconnection to said conductive element.

79. A method as recited in claim 1, comprising:

forming a conductive element on said surface area;

forming said encapsulating member to have a region over said surface area and separated from said conductive element by a gap;

forming an aperture in said encapsulating member in said region over said conductive element; and

forming an interconnection to conductive element through said aperture.

80. A method as recited in claim 79, comprising:

forming said encapsulating member to have a gap of approximately between 0.1 and 1.0 microns.

81. A method as recited in claim 79, comprising:

forming conductive material within said aperture electrically connecting to said conductive element and forms a seal between said encapsulation member and said conductive element.

82. A method as recited in claim 1, comprising:

forming a conductive element on said surface area;

forming said encapsulating member to have a region over said surface area and in contact with said conductive element, but not bonded to said conductive element;

forming an aperture in said encapsulating member in said region over said conductive element; and

forming an interconnection to conductive element through said aperture.

83. A method as recited in claim 82, comprising:

forming a seal that encapsulates said device.

84. A method as recited in claim 82, comprising:

forming a seal that hermetically encapsulates said device.

85. An encapsulated electronic device comprising:

a device carrier including a device and having a first bonding region encompassing said device;

an encapsulating member having a second bonding region bonded to the first bonding region of said device carrier; and

a non-adhesive direct bond formed at near room temperature between the first and second bonding regions thereby to form an encapsulation of the electronic device.

86. A device as recited in claim 85, wherein the non-adhesive direct bond forms a hermetic encapsulation of said device.

87. A device as recited in claim 85, wherein the electronic device includes at least one of an optoelectronic device, a micro-electrical mechanical systems MEMS device, and a radio frequency device.

88. A device as recited in claim 87, wherein said device comprises a concave device.

89. A device as recited in claim 88, wherein the concave device comprises a MEMS concave device.

90. A device as recited in claim 88, wherein a plurality of concave devices are compartmentalized inside the encapsulating member.

91. A device as recited in claim 87, wherein said device comprises a convex device.

92. A device as recited in claim 91, wherein the convex device comprises a MEMS convex device.

93. A device as recited in claim 91, wherein a plurality of convex devices are compartmentalized inside the encapsulating member.

94. A device as recited in claim 85, wherein said bonding regions of said device carrier and said encapsulating member each have a surface roughness of less than 0.5-1 nm.

95. A device as recited in claim 85, wherein said bonding regions of said device carrier and the encapsulating member each have a surface planarity of less than 0.1 μ

m over a 100 μ

m range.

96. A device as recited in claim 85, wherein said device carrier comprises a semiconductor wafer.

97. A device as recited in claim 85, wherein said device carrier comprises a thinned semiconductor wafer.

98. A device as recited in claim 85, wherein the encapsulating member comprises a semiconductor wafer.

99. A device as recited in claim 98, wherein said encapsulating member comprises a semiconductor wafer containing one of a device, circuit and integrated circuit.

100. A device as recited in claim 85, wherein the encapsulating member comprises:

an interposer having at least one through hole configured to provide a relief for said device and including said second bonding region of said encapsulating member; and

a cover configured to bond to said interposer on a third bonding region to thereby seal said cover to said interposer.

101. A device as recited in claim 100, wherein the interposer is fabricated from a semiconductor wafer.

102. A device as recited in claim 100, wherein the cover comprises at least one of a semiconductor wafer and a transparent plate.

103. A device as recited in claim 102, wherein said transparent plate includes at least one of glass, quartz, and sapphire.

104. A device as recited in claim 85, wherein said bond has a strength at near room temperature of at least in a range of 500-2000 mJ/m².

105. A device as recited in claim 85, wherein at least one of said bonding regions of said encapsulating member and said device carrier comprises a dielectric layer.

106. A device as recited in claim 105, wherein the dielectric includes at least one of silicon oxide, aluminum oxide, silicon nitride, a spin-on glass, and a dielectric polymer.

107. A device as recited in claim 85, further comprising at least one of an electrical interconnection and an optical interconnection from outside the encapsulation to said device.

108. A device as recited in claim 107, wherein said electrical interconnection comprises:

a metallized through hole through a base of said device carrier.

109. A device as recited in claim 107, wherein said electrical interconnection comprises:

a metallized through hole through a side wall of said encapsulating member.

110. A device as recited in claim 107, wherein said electrical interconnection comprises:

a metallization under said first bonding region.

111. A device as recited in claim 110, wherein the metallization comprises:

a metal/dielectric/metal structure such that an interleaving dielectric layer of said metal/dielectric/metal structure is substantially planar with said first bonding region and a metal layer of said metal/dielectric/metal structure connects to a metal lead of said electronic device.

112. A device as recited in claim 85, comprising:

said encapsulating member having an aperture located over a conductive element of said device; and

an interconnection formed through said aperture to said device.

113. A device as recited in claim 112, wherein said interconnection seals said encapsulation member to said device carrier.

114. A device as recited in claim 112, wherein said interconnection hermetically seals said encapsulation member to said device carrier.

115. A device as recited in claim 112, wherein said encapsulation contains a vacuum.

116. A device as recited in claim 85, comprising:

said encapsulating member comprising a portion opposed to said first bonding region and separated from said first bonding region by a gap of about 0.1 to 1.0 microns;

an aperture formed in said portion; and

an interconnection formed in said aperture and connected to a conductive region of said device.

117. A device as recited in claim 116, comprising:

said conductive region formed in said surface of said device.

118. A device as recited in claim 116, comprising:

said conductive region formed below said surface of said device.

119. A device as recited in claim 116, wherein said conductive region comprises a conductive formed on a surface of said device.

120. A device as recited in claim 85, comprising:

said encapsulating member comprising a portion opposed to and in contact with said first bonding region, but not bonded to said first bonding region;

an aperture formed in said portion; and

an interconnection formed in said aperture and connected to a conductive region of said device.

121. A device as recited in claim 120, comprising:

said conductive region formed in said surface of said device.

122. A device as recited in claim 120, comprising:

said conductive region formed below said surface of said device.

123. A device as recited in claim 120, wherein said conductive region comprises a conductive formed on a surface of said device.